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ORCIDHua Xiang 0001
Person information
- affiliation: IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
- affiliation (PhD 2004): University of Illinois at Urbana-Champaign, IL, USA
- affiliation (former): University of Texas at Austin, TX, USA
Other persons with the same name
- Hua Xiang — disambiguation page
- Hua Xiang 0002
![[0000-0002-5094-2376]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-5094-2376")
— Wuhan University, School of Mathematics and Statistics, China - Hua Xiang 0003 — University of Tokushima, Faculty of Engineering, Japan
- Hua Xiang 0004 — Chinese University of Hong Kong
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2020 – today
- 2023
[c29]Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam, Jiang Hu:
Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops. ISVLSI 2023: 1-6- 2022
- [j9]Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu:
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3503-3514 (2022) - [c28]Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam:
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. ICCAD 2022: 64:1-64:8 - 2021
- [c27]Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam:
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. ICCAD 2021: 1-9 - 2020
- [c26]Hua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu:
Self-Aligned Double-Patterning Aware Legalization. DATE 2020: 1145-1150 - [c25]Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam:
Routing-Free Crosstalk Prediction. ICCAD 2020: 163:1-163:9 - [c24]Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu:
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. ISPD 2020: 135-142
2010 – 2019
- 2016
- [c23]Hua Xiang, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu:
Gate movement for timing improvement on row based Dual-VDD designs. ISQED 2016: 423-429 - 2014
- [c22]Hua Xiang, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu:
Row Based Dual-VDD Island Generation and Placement. DAC 2014: 125:1-125:6 - 2013
- [c21]Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri:
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. ICCAD 2013: 342-348 - [c20]Hua Xiang, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri:
Depth controlled symmetric function fanin tree restructure. ICCAD 2013: 585-591 - [c19]Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri:
Network flow based datapath bit slicing. ISPD 2013: 139-146 - 2010
- [c18]Minsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri:
History-based VLSI legalization using network flow. DAC 2010: 286-291 - [c17]Hua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho:
Logical and physical restructuring of fan-in trees. ISPD 2010: 67-74
2000 – 2009
- 2008
- [j8]Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 621-632 (2008) - [j7]Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 633-642 (2008) - [j6]Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
Track Routing and Optimization for Yield. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 872-882 (2008) - 2007
- [c16]Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18 - [c15]Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58 - [c14]Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10 - [c13]Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26 - [c12]Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong:
OPC-Friendly Bus Driven Floorplanning. ISQED 2007: 847-852 - 2006
- [j5]Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1754-1762 (2006) - [c11]Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri:
Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492 - 2005
- [j4]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
An algorithm for integrated pin assignment and buffer planning. ACM Trans. Design Autom. Electr. Syst. 10(3): 561-572 (2005) - [c10]Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186 - [c9]Hua Xiang, I-Min Liu, Martin D. F. Wong:
Wire Planning with Bounded Over-the-Block Wires. ISQED 2005: 622-627 - 2004
- [b1]Hua Xiang:
New Strategies for High Performance VLSI Physical Design. University of Illinois Urbana-Champaign, USA, 2004 - [j3]Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu:
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 141-147 (2004) - [j2]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Bus-driven floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11): 1522-1530 (2004) - [c8]Hua Xiang, Kai-Yuan Chao, D. F. Wong:
An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46 - 2003
- [j1]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Min-cost flow-based algorithm for simultaneous pin assignment and routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 870-878 (2003) - [c7]Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun:
Wire type assignment for FPGA routing. FPGA 2003: 61-67 - [c6]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Bus-Driven Floorplanning. ICCAD 2003: 66-73 - 2002
- [c5]Hua Xiang, D. F. Wong, Xiaoping Tang:
An algorithm for integrated pin assignment and buffer planning. DAC 2002: 584-589 - [c4]Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu:
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-475 - [c3]Hua Xiang, Kai-Yuan Chao, D. F. Wong:
ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74 - 2001
- [c2]Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong:
A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD 2001: 49-56 - [c1]Hua Xiang, Xiaoping Tang, D. F. Wong:
An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD 2001: 232-
Coauthor Index
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