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Deog-Kyoon Jeong
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Publications
- 2020
- [j90]Sangyoon Lee, Han-Gon Ko, Joo-Hyung Chae, Soyeong Shin, Jaekwang Yun, Deog-Kyoon Jeong, Suhwan Kim:
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020) - [j89]Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong:
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1814-1818 (2020) - 2019
- [c54]Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong:
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits 2019: 94- - 2018
- [j68]Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim:
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1894-1898 (2018) - 2015
- [c34]Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim:
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. A-SSCC 2015: 1-4 - 2014
- [j47]Jong-Kwan Woo, Hyunjoong Lee, Hwi-Cheol Kim, Deog-Kyoon Jeong, Suhwan Kim:
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 585-592 (2014) - 2013
- [j45]Daeyong Shim, Hyunsik Jeong, Hyunjoong Lee, Cyuyeol Rhee, Deog-Kyoon Jeong, Suhwan Kim:
A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM. IEEE J. Solid State Circuits 48(10): 2550-2557 (2013) - 2011
- [j44]Heesoo Song, Deok-Soo Kim, Do-Hwan Oh, Suhwan Kim, Deog-Kyoon Jeong:
A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. IEEE J. Solid State Circuits 46(2): 424-434 (2011) - [c13]Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog-Kyoon Jeong, Suhwan Kim:
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. ISSCC 2011: 494-496 - 2010
- [j40]Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, Deog-Kyoon Jeong:
A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. IEEE J. Solid State Circuits 45(11): 2300-2311 (2010) - 2009
- [j36]Young-Deok Kim, Hyun-Seok Ahn, Suhwan Kim, Deog-Kyoon Jeong:
A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1221-1230 (2009) - [j34]Jong-Kwan Woo, Dong-Yong Shin, Deog-Kyoon Jeong, Suhwan Kim:
High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer. IEEE Trans. Consumer Electron. 55(3): 1431-1438 (2009) - [c11]Nan Xing, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim:
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. SoCC 2009: 43-46 - 2007
- [j29]Hoesam Jeong, Byoung-Joo Yoo, Cheol Kyu Han, Sang-Yoon Lee, Kang-Yoon Lee, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. IEEE J. Solid State Circuits 42(6): 1318-1327 (2007) - [c9]Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. ISSCC 2007: 222-598 - 2006
- [c8]Young-Deok Kim, Hyun-Seok Ahn, Joon-Young Park, Suhwan Kim, Deog-Kyoon Jeong:
A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification. ISSCC 2006: 587-596
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