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ORCIDJordi Madrenas
- > Home > Persons > Jordi Madrenas
Publications
- 2017
[c45]Javier Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
:
Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration. ARM@Middleware 2017: 4:1-4:7- 2009
- [c26]Javier Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany:
Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture. ReConFig 2009: 445-450 - 2007
- [c19]Jose Antonio Casas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany:
A Novel Hardware Architecture for Self-adaptive Systems. AHS 2007: 592-599 - [i1]Alejandro Chinea Manrique De Lara, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany:
Improving the Performance of PieceWise Linear Separation Incremental Algorithms for Practical Hardware Implementations. CoRR abs/0712.3654 (2007) - 2000
- [c12]Jordi Madrenas, Eduard Alarcón, Jordi Cosp, Juan Manuel Moreno, Alberto Poveda, Joan Cabestany:
Mixed-signal VLSI for neural and fuzzy sequential processors. ISCAS 2000: 389-392 - 1999
- [c11]Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, E. Cantó, Rafal Kielbik, Julio Faura, Josep Maria Insenser:
Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration. Evolvable Hardware 1999: 182-187 - 1998
- [c10]Juan Manuel Moreno, Jordi Madrenas, Julio Faura, E. Cantó, Joan Cabestany, Josep Maria Insenser:
Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices. ICES 1998: 345-355 - 1997
- [c9]Juan Manuel Moreno, Jordi Madrenas, Eduard Alarcón, Joan Cabestany:
Analog Sequential Architecture for Neuro-Fuzzy Models VLSI Implementation. ICANN 1997: 1199-1204 - [c8]Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, J. R. Laúna:
Practical Design Methodology for Commercial Automatic Coin Recognizers Based on Neural Decision Engines. ICONIP (1) 1997: 662-665 - [c7]Alejandro Chinea Manrique De Lara, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany:
Improving the Performance of Piecewise Linear Separation Incremental Algorithms for Practical Hardware Implementations. IWANN 1997: 607-616 - [c6]Jordi Madrenas, Gregorio Ruiz, Juan Manuel Moreno, Joan Cabestany:
Synthesis and Optimization of a Bit-Serial Pipeline Kernel Processor. IWANN 1997: 801-810 - [c5]Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, J. R. Laúna:
Using Classical and Evolutive Neural Models in Industrial Applications: A Case Study for an Automatic Coin Classifier. IWANN 1997: 922-931 - 1995
- [c4]Josep Cugueró, Jordi Madrenas, Juan Manuel Moreno, Joan Cabestany:
Derivation of a new criterion function based on an information measure for improving piecewise linear separation incremental algorithms. ESANN 1995 - [c3]Juan Manuel Moreno, F. X. Vazquez, Francisco Castillo, Jordi Madrenas, Joan Cabestany:
A deterministic method for establishing the initial conditions in the RCE algorithm. ESANN 1995 - [c1]Juan Manuel Moreno, Jordi Madrenas, S. San Anselmo, Francisco Castillo, Joan Cabestany:
Digital Hardware Implementation of ROI Incremental Algorithms. IWANN 1995: 761-770 - 1994
- [j1]Juan Manuel Moreno, Francisco Castillo, Joan Cabestany, Jordi Madrenas, Andrzej Napieralski:
An analog systolic neural processing architecture. IEEE Micro 14(3): 51-59 (1994)
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