Woo-Rham Bae

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Eric Chang

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Publications

2022
[j23]
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Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woorham Bae, Sean Huang, Vladimir M. Milovanovic, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. IEEE J. Solid State Circuits 57(1): 140-152 (2022)
2021
[j21]
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  - journals/tcasI/HanBCWNA21
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Jaeduk Han, Woo-Rham Bae, Eric Chang, Zhongkai Wang, Borivoje Nikolic, Elad Alon:
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1012-1022 (2021)
[c22]
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  - conf/isscc/SchmidtWWCOBHFR21
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Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. ISSCC 2021: 58-60
2019
[j17]
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  - journals/jssc/BaileyRHLCMWMIW19
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Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019)
[c19]
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Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon:
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC 2019: 1-4
2018
[c18]
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  - conf/asscc/BaileyHRLCMWMIW18
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Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC 2018: 285-288
[c17]
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  - conf/cicc/ChangHBWNNA18
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Eric Chang, Jaeduk Han, Woo-Rham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje Nikolic, Elad Alon:
BAG2: A process-portable framework for generator-based AMS circuit design. CICC 2018: 1-8

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