Gyu-Seob Jeong

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Gyungock Kim

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Publications

2018
[j13]
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Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 436-440 (2018)
[j12]
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Gyu-Seob Jeong, Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han-Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018)
[j11]
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Hong-Seok Choi, Jeongho Hwang, Gyu-Seob Jeong, Gyungock Kim, Deog-Kyoon Jeong:
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1824-1828 (2018)
2016
[j5]
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Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park, Joonbae Park, Gyungock Kim, Deog-Kyoon Jeong:
20-Gb/s 5-V_PP and 25-Gb/s 3.8-V_PP Area-Efficient Modulator Drivers in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1034-1038 (2016)
2015
[j2]
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Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015)
2014
[c3]
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Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC 2014: 101-104

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