Min Zhao 0001

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Rajendran Panda

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Publications

2010
[j7]
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Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1342-1353 (2010)
2008
[c20]
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  - conf/isqed/YeZPLH08
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Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu:
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632
2007
[c19]
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  - conf/dac/ZhaoPRFMCSY07
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Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan:
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC 2007: 162-167
[c18]
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  - conf/iccad/YeLZPH07
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Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631
[c17]
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  - conf/iccad/FuPRSZ07
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Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao:
A novel technique for incremental analysis of on-chip power distribution networks. ICCAD 2007: 817-823
2006
[j5]
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  - journals/tcad/ZhaoFZSP06
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Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 144-154 (2006)
[c16]
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  - conf/dac/ZhaoPSYF06
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Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu:
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC 2006: 217-222
2004
[c12]
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  - conf/dac/ZhaoFZSP04
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Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power supply pads and pins. DAC 2004: 165-170
2003
[j4]
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  - journals/tcad/HuBZGZPS03
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Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 49-66 (2003)
[c10]
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  - conf/aspdac/AgarwalBZSZGP03
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Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda:
Statistical delay computation considering spatial correlations. ASP-DAC 2003: 271-276
[c9]
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  - conf/iscas/HuBZGZPS03
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Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671
2002
[j3]
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  - journals/tcad/ZhaoPSB02
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Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw:
Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 159-168 (2002)
[c8]
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  - conf/iccad/HuBZGZPS02
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Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227
[c7]
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  - conf/tau/ZhaoGZFPRA02
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Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal:
Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 22-28
2000
[c4]
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  - conf/dac/ZhaoPSECB00
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Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw:
Hierarchical analysis of power distribution networks. DAC 2000: 150-155

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