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Muhammad Ali Awan

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Pedro F. Souto

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Publications

2022
[j10]
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Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Eduardo Tovar:
Response time analysis of memory-bandwidth-regulated multiframe mixed-criticality systems. J. Syst. Archit. 123: 102346 (2022)
[c18]
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Syed Aftab Rashid, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Eduardo Tovar:
Cache-aware Schedulability Analysis of PREM Compliant Tasks. DATE 2022: 1269-1274
[c17]
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Ishfaq Hussain, Pedro F. Souto, Konstantinos Bletsas, Muhammad Ali Awan, Eduardo Tovar:
Schedulability analysis for CAN bus messages of periodically-varying size. WFCS 2022: 1-8
2021
[j9]
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  - journals/rts/HussainASBAT21
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Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Response time analysis of multiframe mixed-criticality systems with arbitrary deadlines. Real Time Syst. 57(1-2): 141-189 (2021)
2019
[j8]
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Muhammad Ali Awan, Pedro F. Souto, Benny Akesson, Konstantinos Bletsas, Eduardo Tovar:
Uneven memory regulation for scheduling IMA applications on multi-core platforms. Real Time Syst. 55(2): 248-292 (2019)
[j7]
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Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Akesson, Eduardo Tovar:
Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets. ACM Trans. Embed. Comput. Syst. 18(5s): 109:1-109:23 (2019)
[c16]
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Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Memory Bandwidth Regulation for Multiframe Task Sets. RTCSA 2019: 1-11
[c15]
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Ishfaq Hussain, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Response time analysis of multiframe mixed-criticality systems. RTNS 2019: 8-18
2018
[j6]
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Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact). Dagstuhl Artifacts Ser. 4(2): 05:1-05:3 (2018)
[c14]
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Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Mixed-criticality scheduling with memory bandwidth regulation. DATE 2018: 1277-1282
[c13]
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Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar:
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers. ECRTS 2018: 2:1-2:22
[c12]
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Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Akesson, Eduardo Tovar:
Mixed-Criticality Scheduling with Dynamic Memory Bandwidth Regulation. RTCSA 2018: 111-117
2017
[c11]
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  - conf/arcs/AwanBST17
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Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Eduardo Tovar:
Semi-partitioned Mixed-Criticality Scheduling. ARCS 2017: 205-218
[c10]
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Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Akesson, Eduardo Tovar:
Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache. ECRTS 2017: 18:1-18:21
[i1]
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Muhammad Ali Awan, Konstantinos Bletsas, Pedro F. Souto, Benny Akesson, Eduardo Tovar:
Mixed-criticality Scheduling with Dynamic Redistribution of Shared Cache. CoRR abs/1704.08876 (2017)

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