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John Wickerson
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Publications
- 2023
- [j20]Jianyi Cheng, Estíbaliz Fraca, John Wickerson, George A. Constantinides:
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers 72(11): 3300-3313 (2023) - [j19]Jianyi Cheng, Lana Josipovic, John Wickerson, George A. Constantinides:
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(4): 55:1-55:32 (2023) - 2022
- [j16]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides:
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71(4): 933-946 (2022) - [j14]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [j13]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis. ACM Trans. Design Autom. Electr. Syst. 27(4): 30:1-30:26 (2022) - [c39]Jianyi Cheng, John Wickerson, George A. Constantinides:
Dynamic C-Slow Pipelining for HLS. FCCM 2022: 1-10 - [c37]Jianyi Cheng, John Wickerson, George A. Constantinides:
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA 2022: 89-100 - [c36]Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson:
Dynamic Inter-Block Scheduling for HLS. FPL 2022: 243-252 - 2021
- [j9]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Global Analysis of C Concurrency in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 24-37 (2021) - [c35]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Scheduling in High-Level Synthesis. FCCM 2021: 195-203 - [c33]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Optimization for High-Level Synthesis. FPGA 2021: 145 - [c31]Jianyi Cheng, John Wickerson, George A. Constantinides:
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL 2021: 341-346 - 2020
- [j7]He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 516-529 (2020) - [c25]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298 - [c24]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Precise Pointer Analysis in High-Level Synthesis. FPL 2020: 220-224 - 2019
- [i3]He Li, James J. Davis, John Wickerson, George A. Constantinides:
ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR abs/1910.00271 (2019) - 2018
- [j5]Nadesh Ramanathan, John Wickerson, George A. Constantinides:
Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware. IEEE Trans. Computers 67(7): 992-1006 (2018) - [j4]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1802-1815 (2018) - [c21]He Li, James J. Davis, John Wickerson, George A. Constantinides:
Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH 2018: 107-114 - [c20]Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Concurrency-Aware Thread Scheduling for High-Level Synthesis. FCCM 2018: 101-108 - 2017
- [c18]Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides:
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. ACSSC 2017: 126-130 - [c16]Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides:
Hardware Synthesis of Weakly Consistent C Concurrency. FPGA 2017: 169-178 - [c15]Junyi Liu, John Wickerson, George A. Constantinides:
Tile size selection for optimized memory reuse in high-level synthesis. FPL 2017: 1-8 - [c14]He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-precision constant-hardware iterative compute. FPT 2017: 73-79 - [c13]John Wickerson, Mark Batty, Tyler Sorensen, George A. Constantinides:
Automatically comparing memory consistency models. POPL 2017: 190-204 - 2016
- [c12]Junyi Liu, John Wickerson, George A. Constantinides:
Loop Splitting for Efficient Pipelining in High-Level Synthesis. FCCM 2016: 72-79 - [c11]Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides:
A Case for Work-stealing on FPGAs with OpenCL Atomics. FPGA 2016: 48-53 - [c10]Xitong Gao, John Wickerson, George A. Constantinides:
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. FPGA 2016: 234-243 - [c9]Yiren Zhao, John Wickerson, George A. Constantinides:
An efficient implementation of online arithmetic. FPT 2016: 69-76 - [c8]Andrea Picciau, Gordon E. Inggs, John Wickerson, Eric C. Kerrigan, George A. Constantinides:
Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs. HiPC 2016: 183-192 - 2015
- [c5]Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George A. Constantinides:
Custom-sized caches in application-specific memory hierarchies. FPT 2015: 144-151
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