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Yves Bertrand
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Publications
- 2009
- [c64]Florence Azaïs, Yves Bertrand, Michel Renovell:
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS 2009: 158-163 - 2008
- [c61]Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell:
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS 2008: 233-238 - 2005
- [j23]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. 21(3): 291-298 (2005) - [j21]Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005) - 2004
- [j18]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. 20(3): 257-267 (2004) - [j17]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. 20(4): 375-387 (2004) - 2003
- [j16]Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Des. Test Comput. 20(1): 60-67 (2003) - [j15]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. 19(4): 377-386 (2003) - [j14]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. 19(4): 469-479 (2003) - [j13]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
A-to-D converters static error detection from dynamic parameter measurement. Microelectron. J. 34(10): 945-953 (2003) - [c53]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173 - [c52]Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209 - 2002
- [j12]Michel Renovell, Florence Azaïs, Yves Bertrand:
Improving Defect Detection in Static-Voltage Testing. IEEE Des. Test Comput. 19(6): 83-89 (2002) - [c49]Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival:
European Network for Test Education. DELTA 2002: 230-234 - [c48]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling gate oxide short defects in CMOS minimum transistors. ETW 2002: 15-20 - [c47]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
A high accuracy triangle-wave signal generator for on-chip ADC testing. ETW 2002: 89-94 - [c45]Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski:
Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW 2002: 174-179 - 2001
- [j10]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electron. Test. 17(2): 139-147 (2001) - [j9]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electron. Test. 17(3-4): 255-266 (2001) - [j7]André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand:
On the detectability of CMOS floating gate transistor faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 116-128 (2001) - [c43]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595 - [c42]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Analog BIST Generator for ADC Testing. DFT 2001: 338-346 - [c41]Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436 - [c39]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048 - [c38]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW 2001: 112-117 - [c37]Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW 2001: 266-272 - [c36]Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271 - 2000
- [j6]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electron. Test. 16(3): 259-267 (2000) - [c33]Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83 - [c32]Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-230 - [c30]Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs:
On the Temperature Dependencies of Analog BIST. LATW 2000: 88-93 - [c29]Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW 2000: 118-122 - [c28]Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254 - 1999
- [j3]Michel Renovell, Florence Azaïs, Yves Bertrand:
Detection of Defects Using Fault Model Oriented Test Sequences. J. Electron. Test. 14(1-2): 13-22 (1999) - [c25]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
Functional and structural testing of switched-current circuits. ETW 1999: 22-27 - [c24]Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486 - [c23]Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival:
A Successful Distance-Learning Experience for IC Test Education. MSE 1999: 20-21 - 1998
- [c22]Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377 - [c21]Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387 - [c20]Michel Renovell, Florence Azaïs, Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821 - [c17]Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin:
Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375 - 1997
- [c15]Michel Renovell, Florence Azaïs, Yves Bertrand:
On-chip analog output response compaction. ED&TC 1997: 568-572 - 1996
- [c12]Michel Renovell, Florence Azaïs, Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59 - 1995
- [c9]Michel Renovell, Florence Azaïs, Yves Bertrand:
A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119
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