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Jian-Yi Meng

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Chen Chen 0058

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Publications

2020
[c7]
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  - conf/hotchips/0058XLSGLLHLCLP20
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Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi:
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. Hot Chips Symposium 2020: 1-19
[c6]
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  - conf/isca/ChenXLSGLLHLCLP20
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Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng, Xiaolang Yan, Yuan Xie, Xiaoning Qi:
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. ISCA 2020: 52-64
2018
[j23]
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  - journals/ieiceee/HeMCXC18
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  - https://dblp.org/rec/journals/ieiceee/HeMCXC18
Yan He, Jianyi Meng, Zhijian Chen, Xiaoyan Xiang, Chen Chen:
An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs. IEICE Electron. Express 15(3): 20171229 (2018)
2017
[j15]
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  - journals/ieiceee/ZhuXCM17
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Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. IEICE Electron. Express 14(8): 20170218 (2017)
[j14]
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  - journals/ieiceee/WangCXM17
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Sheng Wang, Chen Chen, Xiaoyan Xiang, Jianyi Meng:
A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs. IEICE Electron. Express 14(11): 20170353 (2017)
[j8]
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  - journals/tvlsi/WangCXM17
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Sheng Wang, Chen Chen, Xiaoyan Xiang, Jian-Yi Meng:
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 1993-2006 (2017)
[j7]
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  - journals/tvlsi/YongXCM17
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Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3534-3538 (2017)
[c5]
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  - conf/asicon/YongXCM17
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Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A new error masking flip-flop with one cycle correction penalty. ASICON 2017: 72-75
[c4]
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  - conf/asicon/ChenWXCM17
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Xiaopei Chen, Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A light-weight energy-efficient resilient circuit for variation tolerance. ASICON 2017: 815-818
2016
[j6]
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  - journals/chinaf/ZhaoCCM16
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Chaojun Zhao, Chen Chen, Zhijian Chen, Jianyi Meng:
Value locality based storage compression memory architecture for ECG sensor node. Sci. China Inf. Sci. 59(4): 042401:1-042401:11 (2016)
[j3]
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  - journals/ieiceee/HaoXCMDY16
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Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng, Yong Ding, Xiaolang Yan:
EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. IEICE Electron. Express 13(16): 20160682 (2016)
[j2]
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  - journals/ieiceee/YongXMC16
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Zhenqiang Yong, Xiaoyan Xiang, Jianyi Meng, Chen Chen:
TBCT: Time-Borrowing and Clock Token based error correction and its application in microprocessor. IEICE Electron. Express 13(20): 20160766 (2016)
2015
[c3]
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  - conf/asicon/HaoXCM15
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Ziyi Hao, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A timing failure tolerance design with in-field simultaneous error detection and correction. ASICON 2015: 1-4
[c2]
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Sheng Wang, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
An energy-efficient microprocessor using multilevel error correction for timing error tolerance. ASICON 2015: 1-4
[c1]
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  - conf/asicon/ZhuXCM15
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Tao-Tao Zhu, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. ASICON 2015: 1-4

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