Ken Takeuchi

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Yoshiaki Deguchi

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Publications

2019
[j54]
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Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. IEEE J. Solid State Circuits 54(3): 745-754 (2019)
[j52]
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  - journals/jssc/DeguchiNHT19
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Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi:
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition. IEEE J. Solid State Circuits 54(6): 1800-1811 (2019)
[c59]
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  - conf/asscc/SuzukiMWNDMT19
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Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi:
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. A-SSCC 2019: 231-234
2018
[j48]
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  - journals/jssc/DeguchiST18
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Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi:
Write and Read Frequency-Based Word-Line Batch V_TH Modulation for 2-D and 3-D-TLC NAND Flash Memories. IEEE J. Solid State Circuits 53(10): 2917-2926 (2018)
[c53]
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  - conf/cicc/NakamuraDT18
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Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories. CICC 2018: 1-4
[c51]
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  - conf/essderc/SuzukiDNT18
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Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi:
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. ESSDERC 2018: 150-153
[c49]
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  - conf/irps/SuzukiDNMT18
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Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi:
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs. IRPS 2018: 7-1
[c47]
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  - conf/iscas/HayakawaNDMT18
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Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda, Ken Takeuchi:
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. ISCAS 2018: 1-5
[c45]
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Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. ISCAS 2018: 1-5
2017
[c39]
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  - conf/asscc/WatanabeDT17
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Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi:
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. A-SSCC 2017: 157-160
[c38]
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  - conf/asscc/DeguchiT17
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Yoshiaki Deguchi, Ken Takeuchi:
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. A-SSCC 2017: 161-164
[c37]
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  - conf/cicc/DeguchiNKT17
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Yoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi:
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. CICC 2017: 1-4

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