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Manuel E. Acacio
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Publications
- 2015
- [j27]Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers 64(6): 1534-1547 (2015) - 2014
- [j23]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25(5): 1359-1369 (2014) - 2013
- [j20]J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(1): 59-71 (2013) - [j19]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(11): 2192-2201 (2013) - 2012
- [j18]J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. 8(4): 31:1-31:20 (2012) - [j17]Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61(5): 593-606 (2012) - [j16]José M. Cecilia, José L. Abellán, Juan Fernández, Manuel E. Acacio, José M. García, Manuel Ujaldon:
Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE. J. Supercomput. 62(2): 787-803 (2012) - [c52]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA 2012: 141-152 - [c50]Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García:
ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED 2012: 51-56 - 2011
- [c46]Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT 2011: 203-204 - [c45]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP 2011: 73-82 - [c44]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS 2011: 53-62 - [c43]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops 2011: 700-707 - 2010
- [j14]Alberto Ros, Manuel E. Acacio, José M. García:
A scalable organization for distributed directories. J. Syst. Archit. 56(2-3): 77-87 (2010) - [j10]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. IEEE Trans. Parallel Distributed Syst. 21(8): 1117-1131 (2010) - [j9]Alberto Ros, Manuel E. Acacio, José M. García:
A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 21(12): 1779-1792 (2010) - [c39]Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato:
EMC2: Extending Magny-Cours coherence for large-scale servers. HiPC 2010: 1-10 - 2009
- [c35]Alberto Ros, Manuel E. Acacio, José M. García:
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT 2009: 11-27 - [c33]Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García:
Distance-aware round-robin mapping for large NUCA caches. HiPC 2009: 79-88 - [c32]J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco:
Speculation-based conflict resolution in hardware transactional memory. IPDPS 2009: 1-12 - 2008
- [j8]Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García:
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. 68(11): 1413-1424 (2008) - [j6]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distributed Syst. 19(8): 1044-1056 (2008) - [c30]Alberto Ros, Manuel E. Acacio, José M. García:
Scalable Directory Organization for Tiled CMP Architectures. CDES 2008: 112-118 - [c28]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN 2008: 267-276 - [c27]J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC 2008: 541-554 - [c26]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC 2008: 555-568 - [c23]Alberto Ros, Manuel E. Acacio, José M. García:
DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS 2008: 1-11 - [c22]J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco:
Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP 2008: 30-37 - 2007
- [j5]Gregorio Bernabé, Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José González:
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Comput. 33(1): 54-72 (2007) - [c18]Alberto Ros, Manuel E. Acacio, José M. García:
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC 2007: 147-160 - [c17]Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato:
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA 2007: 157-168 - 2006
- [c16]Alberto Ros, Manuel E. Acacio, José M. García:
An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers 2006: 321-330 - [c15]Francisco J. Villa, Manuel E. Acacio, José M. García:
On the Evaluation of Dense Chip-Multiprocessor Architectures. ICSAMOS 2006: 21-27 - 2005
- [j4]Francisco J. Villa, Manuel E. Acacio, José M. García:
Evaluating IA-32 web servers through simics: a practical experience. J. Syst. Archit. 51(4): 251-264 (2005) - [j3]Manuel E. Acacio, José González, José M. García, José Duato:
A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. 16(1): 67-79 (2005) - [c14]Alberto Ros, Manuel E. Acacio, José M. García:
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par 2005: 582-591 - [c13]Francisco J. Villa, Manuel E. Acacio, José M. García:
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. HPCC 2005: 213-222 - [c12]Ricardo Fernández Pascual, José M. García, Gregorio Bernabé, Manuel E. Acacio:
Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. PDP 2005: 76-83 - 2004
- [j2]Manuel E. Acacio, José González, José M. García, José Duato:
An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Trans. Parallel Distributed Syst. 15(8): 755-768 (2004) - [c11]Francisco J. Villa, Manuel E. Acacio, José M. García:
On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. International Conference on Computational Science 2004: 541-544 - 2002
- [j1]Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel:
MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. Future Gener. Comput. Syst. 18(3): 317-333 (2002) - [c10]Manuel E. Acacio, José González, José M. García, José Duato:
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. IEEE PACT 2002: 155-164 - [c9]Manuel E. Acacio, José González, José M. García, José Duato:
A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. IPDPS 2002 - [c8]Manuel E. Acacio, José González, José M. García, José Duato:
Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. PDP 2002: 368-375 - [c7]Manuel E. Acacio, José González, José M. García, José Duato:
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. SC 2002: 1:1-1:12 - 2001
- [c6]Manuel E. Acacio, José González, José M. García, José Duato:
A New Scalable Directory Architecture for Large-Scale Multiprocessors. HPCA 2001: 97-106 - 1999
- [c5]Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel:
An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. ACPC 1999: 570-571 - [c4]Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte:
P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. IPPS/SPDP 1999: 563-568 - [c3]Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio:
The Parallel EM Algorithm and its Applications in Computer Vision. PDPTA 1999: 571-578 - [c2]Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel:
A Performance Evaluation of P-EDR in Different Parallel Environments. PDPTA 1999: 744-750 - [c1]Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte:
The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. PDPTA 1999: 1730-1736
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