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Iuliana Bacivarov
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Publications
- 2006
- [c4]Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya:
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. DATE Designers' Forum 2006: 166-171 - 2005
- [j1]Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya:
ChronoSym: a new approach for fast and accurate SoC cosimulation. Int. J. Embed. Syst. 1(1/2): 103-111 (2005) - [c3]Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya:
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. ASP-DAC 2005: 969-972 - 2003
- [c2]Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya:
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. DATE 2003: 10550-10555 - [p1]Sungjoo Yoo, Gabriela Nicolescu, Iuliana Bacivarov, Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya:
Multi-Level Software Validation for NoC. Networks on Chip 2003: 261-279 - 2002
- [c1]Iuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya:
Timed HW-SW cosimulation using native execution of OS and application SW. HLDVT 2002: 51-56
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last updated on 2023-09-27 22:48 CEST by the dblp team
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