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Atsushi Kurokawa
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Publications
- 2014
- [j23]Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue:
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1059-1074 (2014) - 2013
- [c13]Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue:
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. ISCAS 2013: 1712-1715 - 2012
- [j22]Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue:
Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. J. Circuits Syst. Comput. 21(6) (2012) - 2011
- [j21]Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue:
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(5): 1201-1209 (2011) - 2010
- [j18]Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 250-260 (2010) - 2009
- [j16]Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue:
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2531-2539 (2009) - 2007
- [c10]Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570 - 2006
- [j12]Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue:
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 840-846 (2006) - [j11]Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 847-855 (2006) - [j10]Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 856-864 (2006) - 2005
- [j8]Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao:
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(10): 2562-2569 (2005) - [j7]Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(11): 3180-3187 (2005) - [j6]Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue:
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3367-3374 (2005) - [j5]Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao:
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3412-3420 (2005) - [j4]Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3453-3462 (2005) - [j3]Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3471-3478 (2005) - [c7]Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue:
Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798 - [c6]Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158 - [c5]Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591 - 2004
- [c3]Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
Efficient capacitance extraction method for interconnects with dummy fills. CICC 2004: 485-488
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