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José Luis Risco-Martín

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with David Cuesta

> Home > Persons > José Luis Risco-Martín

Publications

2024
[i19]
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  dblp key:
  - journals/corr/abs-2402-14627
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  - https://dblp.org/rec/journals/corr/abs-2402-14627
David Cuesta, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo:
Thermal-Aware Floorplanner for 3D IC, including TSVs, Liquid Microchannels and Thermal Domains Optimization. CoRR abs/2402.14627 (2024)
2015
[j21]
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  dblp key:
  - journals/asc/CuestaRAH15
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  - https://dblp.org/rec/journals/asc/CuestaRAH15
David Cuesta, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo:
Thermal-aware floorplanner for 3D IC, including TSVs, liquid microchannels and thermal domains optimization. Appl. Soft Comput. 34: 164-177 (2015)
2013
[j13]
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  dblp key:
  - journals/integration/CuestaRAH13
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  - https://dblp.org/rec/journals/integration/CuestaRAH13
David Cuesta, José Luis Risco-Martín, José L. Ayala, José Ignacio Hidalgo:
3D thermal-aware floorplanner using a MOEA approximation. Integr. 46(1): 10-21 (2013)
2012
[j10]
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  dblp key:
  - journals/mam/CuestaRA12
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  - https://dblp.org/rec/journals/mam/CuestaRA12
David Cuesta, José Luis Risco-Martín, José L. Ayala:
3D thermal-aware floorplanner using a MILP approximation. Microprocess. Microsystems 36(5): 344-354 (2012)
2011
[c22]
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  dblp key:
  - conf/gecco/GomezRAH11
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  - https://dblp.org/rec/conf/gecco/GomezRAH11
David Cuesta Gómez, José Luis Risco-Martín, José Luis Ayala, José Ignacio Hidalgo:
A combination of evolutionary algorithm and mathematical programming for the 3d thermal-aware floorplanning problem. GECCO 2011: 1731-1738
[c20]
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  dblp key:
  - conf/latw/CuestaRAA11
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  - https://dblp.org/rec/conf/latw/CuestaRAA11
David Cuesta, José L. Risco-Martín, José L. Ayala, David Atienza:
3D Thermal-aware floorplanner for many-core single-chip systems. LATW 2011: 1-6

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