Bulusu Anand

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Baljit Kaur

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Publications

2016
[j6]
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Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand:
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53: 45-55 (2016)
2015
[c13]
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  - conf/vdat/ChaurasiyaBSKA15
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Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand:
Timing model for two stage buffer and its application in ECSM characterization. VDAT 2015: 1-6
2014
[j4]
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  - journals/tcas/KaurAMA14
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Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand:
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3407-3415 (2014)
2013
[c8]
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  - conf/isqed/KaurMMA13
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Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand:
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED 2013: 665-669
2012
[c6]
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  - conf/isqed/KaurVMDA12
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Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand:
An accurate current source model for CMOS based combinational logic cell. ISQED 2012: 561-565
2011
[c2]
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  - conf/isqed/MiryalaKAM11
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Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas:
Efficient nanoscale VLSI standard cell library characterization using a novel delay model. ISQED 2011: 458-463

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