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ORCIDMing-che Lai
- > Home > Persons > Ming-che Lai
Publications
- 2014
[j8]Sheng Ma, Natalie D. Enright Jerger
, Zhiying Wang, Ming-che Lai, Libo Huang:
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs. IEEE Trans. Computers 63(3): 529-542 (2014)- 2013
- [j7]Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network. Sci. China Inf. Sci. 56(7): 1-20 (2013) - [j6]Libo Huang, Nong Xiao, Zhiying Wang, Yongwen Wang, Ming-che Lai:
Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP. Parallel Comput. 39(10): 586-602 (2013) - 2011
- [j3]Ming-che Lai, Lei Gao, Sheng Ma, Nong Xiao, Zhiying Wang:
A practical low-latency router architecture with wing channel for on-chip network. Microprocess. Microsystems 35(2): 98-109 (2011) - 2009
- [c16]Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and efficient performance analysis approach based on queuing model for network on chip. ICCAD 2009: 563-570 - 2008
- [c13]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Memory System Design for a Multi-core Processor. CISIS 2008: 601-606 - [c11]Ming-che Lai, Lei Gao, Wei Shi, Zhiying Wang:
Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers. CISIS 2008: 795-800 - [c9]Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai:
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. DAC 2008: 630-633 - [c8]Jianjun Guo, Kui Dai, Ming-che Lai, Zhiying Wang:
The P2P Communication Model for a Local Memory based Multi-core Processor. ICYCS 2008: 1354-1359 - [c7]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Hierarchical memory system design for a heterogeneous multi-core processor. SAC 2008: 1504-1508 - 2007
- [c6]Ming-che Lai, Jianjun Guo, Lv Yasuai, Kui Dai, Zhiying Wang:
The Research of an Embedded Processor Element for Multimedia Domain. MCAM 2007: 267-276 - [c4]Ming-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li:
Template Vertical Dictionary-Based Program Compression Scheme on the TTA. PATMOS 2007: 43-52 - 2006
- [c3]Ming-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang:
A Novel Data-Parallel Coprocessor for Multimedia Signal Processing. ICME 2006: 369-372 - 2005
- [c2]Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang:
Design of a Configurable Embedded Processor Architecture for DSP Functions. ICPADS (2) 2005: 27-31 - 2004
- [c1]Ming-che Lai, Kui Dai, Li Shen, Zhiying Wang:
A New Technique for Program Code Compression in Embedded Microprocessor. ICESS 2004: 158-164
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