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Xiaoyao Liang
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Publications
- 2009
- [j2]Xiaoyao Liang, Gu-Yeon Wei, David M. Brooks:
Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. IEEE Micro 29(1): 127-138 (2009) - [c12]Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David M. Brooks:
Design and test strategies for microarchitectural post-fabrication tuning. ICCD 2009: 84-90 - [c11]Kristen Lovin, Benjamin C. Lee, Xiaoyao Liang, David M. Brooks, Gu-Yeon Wei:
Empirical performance models for 3T1D memories. ICCD 2009: 398-403 - 2008
- [j1]Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks:
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability. IEEE Micro 28(1): 60-68 (2008) - [c9]Xiaoyao Liang, Gu-Yeon Wei, David M. Brooks:
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. ISCA 2008: 191-202 - [c8]Gu-Yeon Wei, David M. Brooks, Ali Durlov Khan, Xiaoyao Liang:
Instruction-driven clock scheduling with glitch mitigation. ISLPED 2008: 357-362 - [c7]Xiaoyao Liang, David M. Brooks, Gu-Yeon Wei:
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency. ISSCC 2008: 404-405 - 2007
- [c6]Xiaoyao Liang, Kerem Turgay, David M. Brooks:
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD 2007: 824-830 - [c5]Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks:
Process Variation Tolerant 3T1D-Based Cache Architectures. MICRO 2007: 15-26 - 2006
- [c4]Xiaoyao Liang, David M. Brooks:
Microarchitecture parameter selection to optimize system performance under process variation. ICCAD 2006: 429-436 - [c3]Xiaoyao Liang, David M. Brooks:
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units. MICRO 2006: 504-514
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