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Rouwaida Kanj
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Publications
- 2023
- [j16]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi:
A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1742-1755 (2023) - 2022
- [j14]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Ali Chehab:
Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5722-5726 (2022) - 2019
- [c39]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi:
Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs. ISCAS 2019: 1-5 - 2018
- [j9]Maria Malik, Rajiv V. Joshi, Rouwaida Kanj, Shupeng Sun, Houman Homayoun, Tong Li:
Sparse Regression Driven Mixture Importance Sampling for Memory Design. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 63-72 (2018) - 2017
- [c36]Adam Issa, Rouwaida Kanj, Ali Chehab, Rajiv V. Joshi:
Yield and energy tradeoffs of an NVLatch design using radial sampling. ICICDT 2017: 1-4 - [c35]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Maria Malik, Ali Chehab:
Regularized logistic regression for fast importance sampling based SRAM yield analysis. ISQED 2017: 119-124 - 2016
- [j7]Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra:
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 968-978 (2016) - [c34]Mohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li, Rajiv V. Joshi:
Efficient analog circuit optimization using sparse regression and error margining. ISQED 2016: 410-415 - 2015
- [j6]Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh:
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 534-543 (2015) - [j5]Rajiv V. Joshi, Rouwaida Kanj:
Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction". IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1380 (2015) - 2014
- [c31]Gerard Touma, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab:
Robust bias temperature instability refresh design and methodology for memory cell recovery. ICICDT 2014: 1-4 - [c30]Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab:
Statistical methodology for modeling non-IID memory fails events. ISQED 2014: 205-211 - [c29]Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi:
Impact of FinFET technology for power gating in nano-scale design. ISQED 2014: 543-547 - 2013
- [c26]Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, D. Lea, D. Sciacca:
Hardware-corroborated Variability-Aware SRAM Methodology. VLSI Design 2013: 344-349 - 2012
- [c25]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif:
Yield estimation via multi-cones. DAC 2012: 1107-1112 - [c24]Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen:
A thermal and process variation aware MTJ switching model and its applications in soft error analysis. ICCAD 2012: 720-727 - [c23]Rouwaida Kanj, Rajiv V. Joshi:
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability. ISQED 2012: 672-678 - [c22]John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver:
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC 2012: 110-111 - 2011
- [j4]Rajiv V. Joshi, Rouwaida Kanj, Vinod Ramadurai:
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 869-882 (2011) - [j3]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design 2011: 471903:1-471903:12 (2011) - [c21]Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Li:
Universal statistical cure for predicting memory loss. ICCAD 2011: 236-239 - [c20]Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif:
Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360 - 2010
- [j2]Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan:
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. IEEE Des. Test Comput. 27(6): 36-45 (2010) - [c19]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED 2010: 337-342 - [c18]Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj:
Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. ISQED 2010: 315-319 - [c17]Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj:
FinFET SRAM Design. VLSI Design 2010: 440-445 - 2009
- [c16]Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif:
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD 2009: 497-504 - [c14]Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka:
Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194 - [c13]Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612 - 2008
- [c12]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92 - [c11]Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif:
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707 - [c10]Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif:
A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809 - 2007
- [c9]Vinod Ramadurai, Rajiv V. Joshi, Rouwaida Kanj:
A Disturb Decoupled Column Select 8T SRAM Cell. CICC 2007: 25-28 - [c8]Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang:
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED 2007: 8-13 - [c7]Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40 - 2006
- [c5]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC 2006: 69-72
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