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Huiyang Zhou
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Publications
- 2019
- [j16]Zhen Lin, Hongwen Dai, Michael Mantor, Huiyang Zhou:
Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution. ACM Trans. Archit. Code Optim. 16(3): 23:1-23:27 (2019) - [c54]Zhen Lin, Mohammad A. Alshboul, Yan Solihin, Huiyang Zhou:
Exploring Memory Persistency Models for GPUs. PACT 2019: 311-323 - [c53]Zhen Lin, Utkarsh Mathur, Huiyang Zhou:
Scatter-and-Gather Revisited: High-Performance Side-Channel-Resistant AES on GPUs. GPGPU@ASPLOS 2019: 2-11 - [c52]Hui Guan, Lin Ning, Zhen Lin, Xipeng Shen, Huiyang Zhou, Seung-Hwan Lim:
In-Place Zero-Space Memory Protection for CNN. NeurIPS 2019: 5735-5744 - [i3]Zhen Lin, Mohammad A. Alshboul, Yan Solihin, Huiyang Zhou:
Exploring Memory Persistency Models for GPUs. CoRR abs/1904.12661 (2019) - [i2]Hui Guan, Lin Ning, Zhen Lin, Xipeng Shen, Huiyang Zhou, Seung-Hwan Lim:
In-Place Zero-Space Memory Protection for CNN. CoRR abs/1910.14479 (2019) - 2018
- [j15]Zhen Lin, Michael Mantor, Huiyang Zhou:
GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP. ACM Trans. Archit. Code Optim. 15(1): 15:1-15:21 (2018) - [c51]Hongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou:
Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls. HPCA 2018: 208-220 - 2017
- [c50]Hongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou:
POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls. PACT 2017: 144-145 - 2016
- [c44]Chen Zhao, Fei Wang, Zhen Lin, Huiyang Zhou, Nanning Zheng:
Selectively GPU Cache Bypassing for Un-Coalesced Loads. ICPADS 2016: 908-915 - [c42]Zhen Lin, Lars Nyland, Huiyang Zhou:
Enabling efficient preemption for SIMT architectures with lightweight context switching. SC 2016: 898-908 - 2015
- [c39]Chao Li, Yi Yang, Zhen Lin, Huiyang Zhou:
Automatic data placement into GPU on-chip memory resources. CGO 2015: 23-33
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