Alan Mishchenko

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Stephen Jang

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Publications

2012
[c57]
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Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen:
Mapping into LUT structures. DATE 2012: 1579-1584
2011
[j13]
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Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4(4): 34:1-34:23 (2011)
[c53]
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Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets:
Delay optimization using SOP balancing. ICCAD 2011: 375-382
2010
[c48]
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  - conf/fpga/MishchenkoBJ10
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Alan Mishchenko, Robert K. Brayton, Stephen Jang:
Global delay optimization using structural choices. FPGA 2010: 181-184
2009
[j10]
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Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko:
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. ACM Trans. Reconfigurable Technol. Syst. 2(2): 14:1-14:24 (2009)
[c44]
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Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160
[c43]
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Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240
2008
[c38]
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  - conf/fpga/JangCCM08
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Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko:
WireMap: FPGA technology mapping for improved routability. FPGA 2008: 47-55
[c36]
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Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang:
Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241

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