John Sartori

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hari Cherupalli

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Publications

2022
[c39]
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Subhash Sethumurugan, Shashank Hegde, Hari Cherupalli, John Sartori:
A scalable symbolic simulation tool for low power embedded systems. DAC 2022: 175-180
2021
[c36]
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  - conf/aspdac/HegdeSCDS21
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Shashank Hegde, Subhash Sethumurugan, Hari Cherupalli, Henry Duwe, John Sartori:
Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems. ASP-DAC 2021: 318-324
2018
[j11]
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Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints. IEEE Micro 38(3): 32-39 (2018)
2017
[j9]
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Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors. ACM Trans. Comput. Syst. 35(3): 9:1-9:33 (2017)
[c31]
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Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors. ASPLOS 2017: 3-16
[c29]
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Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Enabling Effective Module-Oblivious Power Gating for Embedded Processors. HPCA 2017: 157-168
[c28]
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Hari Cherupalli, John Sartori:
Scalable N-worst algorithms for dynamic timing and activity analysis. ICCAD 2017: 585-592
[c27]
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Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Bespoke Processors for Applications with Ultra-low Area and Power Constraints. ISCA 2017: 41-54
[c26]
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Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Software-based gate-level information flow security for IoT systems. MICRO 2017: 328-340
2016
[c25]
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  - conf/iccad/KapareCS16
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Amrut Kapare, Hari Cherupalli, John Sartori:
Automated error prediction for approximate sequential circuits. ICCAD 2016: 82
[c24]
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Hari Cherupalli, Rakesh Kumar, John Sartori:
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems. ISCA 2016: 671-681
2015
[c23]
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Hari Cherupalli, John Sartori:
Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions. ICCAD 2015: 729-735

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