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Hamid Mahmoodi
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Publications
- 2014
- [j28]Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Hooman Farkhani, Dag T. Wisland, Jens Kargaard Madsen, Hamid Mahmoodi, Kaushik Roy:
Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectron. J. 45(1): 23-34 (2014) - 2011
- [c49]Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy:
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD 2011: 326-331 - 2010
- [j18]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. 58(2): 125-137 (2010) - [c45]Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy:
Data-dependant sense-amplifier flip-flop for low power applications. CICC 2010: 1-4 - 2009
- [j17]Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy:
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 33-44 (2009) - 2008
- [j16]Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy:
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electron. Test. 24(6): 577-590 (2008) - [j15]Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A Low-Power SRAM Using Bit-Line Charge-Recycling. IEEE J. Solid State Circuits 43(2): 446-459 (2008) - [j14]Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 174-183 (2008) - 2007
- [j13]Saibal Mukhopadhyay, Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS. IEEE J. Solid State Circuits 42(6): 1370-1382 (2007) - [j12]Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy:
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1957-1966 (2007) - [c31]Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182 - 2006
- [j11]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 183-192 (2006) - [j10]Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 1034-1039 (2006) - [c29]Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670 - [c28]Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia:
Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867 - [c26]Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452 - 2005
- [j9]Hamid Mahmoodi, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits. IEEE J. Solid State Circuits 40(9): 1787-1796 (2005) - [j8]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1859-1880 (2005) - [j7]Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 27-38 (2005) - [j6]Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy:
Low-power scan design using first-level supply gating. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 384-395 (2005) - [j5]Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1286-1295 (2005) - [c25]Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy:
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181 - [c24]Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484 - [c23]Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141 - [c22]Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy:
Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471 - [c20]Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici:
Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224 - [c19]Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214 - [c18]Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176 - [c16]Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy:
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458 - [c15]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495 - [c14]Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy:
A leakage control system for thermal stability during burn-in test. ITC 2005: 10 - [c13]Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy:
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. ITC 2005: 10 - [c11]Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297 - 2004
- [j4]Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy:
Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits 39(2): 348-357 (2004) - [j3]Hamid Mahmoodi-Meimand, Kaushik Roy:
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(3): 495-503 (2004) - [c10]Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy:
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. CICC 2004: 17-20 - [c9]Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy:
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315 - [c8]Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy:
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) 2004: 97-100 - [c7]Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy:
Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13 - [c6]Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy:
A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65 - [c5]Hamid Mahmoodi-Meimand, Kaushik Roy:
Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664 - [c4]Hamid Mahmoodi-Meimand, Kaushik Roy:
Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680 - 2003
- [c3]Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy:
Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59 - 2002
- [j1]Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand:
Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. 11(6): 575-600 (2002) - [c2]Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy:
High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300
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