Jiawei Wang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jun Han 0003

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Publications

2024
[j58]
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Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng:
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1859-1863 (2024)
2023
[j38]
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  - journals/tcasI/ZhangWCHZ23
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Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5242-5253 (2023)
2022
[c41]
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  - conf/iscas/WangWC0Z22
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Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS 2022: 2933-2937
2021
[c34]
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  - conf/asscc/WangYWCHZ21
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Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesizable 0.0060mm² VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. A-SSCC 2021: 1-3

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