Rakesh Malik

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Vigyan Jain

> Home > Persons > Rakesh Malik

Publications

2017
[j2]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/KumarDSBCJTM17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/KumarDSBCJTM17
Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065-mm² 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB. IEEE J. Solid State Circuits 52(7): 1927-1939 (2017)
2016
[c13]
- view
  authority control:
- export record
  dblp key:
  - conf/esscirc/KumarDSBCJTM16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/KumarDSBCJTM16
Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065mm² 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. ESSCIRC 2016: 165-168

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.