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ORCIDRoberto Giorgi
- > Home > Persons > Roberto Giorgi
Publications
- 2009
[e4]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009. ACM 2009, ISBN 978-1-60558-830-8 [contents]- 2008
- [e3]Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008. ACM 2008, ISBN 978-1-60558-243-6 [contents] - 2007
- [e2]Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007. ACM 2007, ISBN 978-1-59593-807-7 [contents] - 2006
- [j9]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News 34(1): 1-2 (2006) - 2005
- [j8]Pierfrancesco Foglia
, Roberto Giorgi, Cosimo Antonio Prete:
Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. J. Parallel Distributed Comput. 65(3): 289-306 (2005) - 2004
- [j7]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Speeding-up multiprocessors running DBMS workloads through coherence protocols. Int. J. High Perform. Comput. Netw. 1(1/2/3): 17-32 (2004) - [e1]Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004. ACM 2004 [contents] - 2002
- [c11]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. NETWORKING Workshops 2002: 134-146 - [c10]Irina Branovic, Roberto Giorgi, Cosimo Antonio Prete:
Web-based training on computer architecture: the case for JCachesim. WCAE 2002: 10 - 2001
- [j5]Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero:
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News 29(5): 9-12 (2001) - [c8]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. HICSS 2001 - 2000
- [c7]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Performance Analysis of Electronic Commerce Multiprocessor Server. HICSS 2000 - 1999
- [j2]Roberto Giorgi, Cosimo Antonio Prete:
PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 10(7): 742-763 (1999) - [c6]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Process Migration Effects on Memory Performance of Multiprocessor. HiPC 1999: 133-142 - 1998
- [c5]Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete:
Analysis of Sharing Overhead in Shared Memory Multiprocessors. HICSS (7) 1998: 776-777 - [c4]Roberto Giorgi, Cosimo Antonio Prete:
An educational environment for designing and performance tuning of embedded systems. WCAE@ISCA 1998: 29 - 1997
- [j1]Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi:
Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. IEEE Concurrency 5(4): 54-68 (1997) - [c3]Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi:
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) 1997: 266-275 - [c2]Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina:
Cache memory design for embedded systems based on program locality analysis. MSE 1997: 16-18 - 1996
- [c1]Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina:
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO 1996: 207-214
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