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ORCIDMasayoshi Yagyu
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2010 – 2019
- 2011
[j3]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura:
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. IEEE J. Solid State Circuits 46(12): 3101-3112 (2011)- [c4]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura:
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150
2000 – 2009
- 2008
- [c3]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi:
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. ISSCC 2008: 98-99 - 2006
- [j2]Tatsuya Kawashimo, Hiroki Yamashita, Masayoshi Yagyu, Fumio Yuki:
A Low-Power Write Driver for Hard Disk Drives. IEICE Trans. Electron. 89-C(11): 1670-1673 (2006) - 2001
- [j1]Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. IEEE J. Solid State Circuits 36(3): 503-509 (2001) - 2000
- [c2]Yuji Yokoyama, Nybutaka Itoh, Masap Katayama, Kazumasa Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Tom Kobayashi, Syuichi Miyaoka, Nobuo Tamba:
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%. CICC 2000: 279-282
1990 – 1999
- 1990
- [c1]Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Minoru Yamada, Akira Masaki:
Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. IJCNN 1990: 527-535
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