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Vivek S. Nandakumar

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affiliation: VLSI-CAD Lab, University of California, Santa Barbara, CA, USA

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Journal Articles

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2014
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Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. IEEE Comput. Archit. Lett. 13(2): 81-84 (2014)
2012
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Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 266-277 (2012)

Conference and Workshop Papers

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2014
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Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. DAC 2014: 137:1-137:6
2011
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Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Layout effects in fine grain 3D integrated regular microprocessor blocks. DAC 2011: 639-644
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Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
Low power, high throughput network-on-chip fabric for 3D multicore processors. ICCD 2011: 453-454
2010
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Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska:
Statistical static timing analysis flow for transistor level macros in a microprocessor. ISQED 2010: 163-170

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