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2020 – today
- 2023
[c10]Yan-Cheng Guo, Wei-Tien Lin, Tuo-Hung Hou, Tian-Sheuan Chang:
FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices. ISCAS 2023: 1-5- [c9]Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou:
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j7]Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou
, Tian-Sheuan Chang, Shyh-Jye Jou:
Hardware-Robust In-RRAM-Computing for Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 547-556 (2022) - [j6]I-Ting Wang, Chih-Cheng Chang, Yen-Yu Chen, Yi-Shin Su, Tuo-Hung Hou:
Two-dimensional materials for artificial synapses: toward a practical application. Neuromorph. Comput. Eng. 2(1): 12003 (2022) - [c8]Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT 2022: 1-4 - [c7]Ming-Chun Hong, Yao-Jen Chang, Yu-Chen Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I-Jung Wang, Sk. Ziaur Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Minn-Tsong Lin, Chih-I Wu, Tuo-Hung Hou:
A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer. VLSI Technology and Circuits 2022: 379-380 - [i4]Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
Hardware-Robust In-RRAM-Computing for Object Detection. CoRR abs/2205.03996 (2022) - 2021
- [j5]Fu-Xiang Liang, I-Ting Wang, Tuo-Hung Hou:
Progress and Benchmark of Spiking Neuron Devices and Circuits. Adv. Intell. Syst. 3(8): 2100007 (2021) - [c6]Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou:
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC 2021: 1-3 - 2020
- [c5]Chih-Pin Lin, Hao-Hua Hsu, Tuo-Hung Hou:
Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering. DRC 2020: 1-2 - [c4]Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri:
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar. ISCAS 2020: 1-5 - [i3]Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri:
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE Using OxRAM Crossbar. CoRR abs/2006.05657 (2020)
2010 – 2019
- 2019
- [c3]Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou:
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. DAC 2019: 30 - 2018
- [j4]Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou:
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 116-124 (2018) - [j3]Jen-Chieh Liu, Tzu-Yun Wu, Tuo-Hung Hou:
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 617-621 (2018) - [i2]Sandeep Kaur Kingra, Vivek Parmar, Che-Chia Chang, Boris Hudec, Tuo-Hung Hou, Manan Suri:
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices. CoRR abs/1811.05772 (2018) - 2017
- [i1]Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou:
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse. CoRR abs/1712.05895 (2017) - 2016
- [j2]Boris Hudec, Chung-Wei Hsu, I-Ting Wang, Wei-Li Lai, Che-Chia Chang, Taifang Wang, Karol Fröhlich, Chia-Hua Ho, Chen-Hsi Lin, Tuo-Hung Hou:
3D resistive RAM cell design for high-density storage class memory - a review. Sci. China Inf. Sci. 59(6): 061403:1-061403:21 (2016) - 2015
- [j1]Chun-Tse Chou, Boris Hudec, Chung-Wei Hsu, Wei-Li Lai, Chih-Cheng Chang, Tuo-Hung Hou:
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM. Microelectron. Reliab. 55(11): 2220-2223 (2015) - [c2]Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD 2015: 194-199 - 2010
- [c1]Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan:
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. SoCC 2010: 461-466
Coauthor Index
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last updated on 2023-11-13 23:27 CET by the dblp team
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