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Ghassem Jaberipur
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2020 – today
- 2025
- [c12]Mohammadreza Najafi, Mohammad K. Fallah, Saeid Gorgin, Ghassem Jaberipur, Jeong-A Lee:
Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture. WoWMoM 2025: 301-303 - 2024
- [j46]Sahar Moradi Cherati
, Ghassem Jaberipur, Leonel Sousa
:
Sparse Matrix-Vector Multiplication Based on Online Arithmetic. IEEE Access 12: 87653-87664 (2024) - [j45]Iraj Moghaddasi
, Ghassem Jaberipur, Danial Javaheri
, Byeong-Gyu Nam
:
RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine. IEEE Access 12: 96552-96564 (2024) - [c11]Zabihollah Ahmadpour, Ghassem Jaberipur, Jeong-A Lee:
Montgomery Modular Multiplication via Single-Base Residue Number Systems. ARITH 2024: 17-23 - [i1]Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee:
Modulo-(22n+1) Arithmetic via Two Parallel n-bit Residue Channels. CoRR abs/2404.08228 (2024) - 2023
- [j44]Ghassem Jaberipur
, Dariush Badri
, Jeong-A Lee
:
A Parallel Prefix Modulo-(2q + 2q-1 + 1) Adder via Diminished-1 Representation of Residues. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3104-3108 (2023) - [c10]Ghassem Jaberipur, Saeid Gorgin, Navid Ahamadian, Jeong-A Lee:
Modulo-(2q - 3) Multiplication with Fully Modular Partial Product Generation and Reduction. ARITH 2023: 68-75 - 2022
- [j43]Armin Belghadr, Ghassem Jaberipur:
Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set. Signal Image Video Process. 16(6): 1443-1454 (2022) - [j42]Zabihollah Ahmadpour
, Ghassem Jaberipur
:
Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels. IEEE Trans. Computers 71(6): 1399-1410 (2022) - [j41]Ghassem Jaberipur
, Farzad Ghazanfari:
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 51-59 (2022) - 2020
- [j40]Behrooz Parhami, Dariush Abedi, Ghassem Jaberipur:
Majority-Logic, its applications, and atomic-scale embodiments. Comput. Electr. Eng. 83: 106562 (2020) - [j39]Zeinab Torabi
, Ghassem Jaberipur, Armin Belghadr:
Fast division in the residue number system {2n + 1, 2n, 2n-1} based on shortcut mixed radix conversion. Comput. Electr. Eng. 83: 106571 (2020) - [j38]Adel Hosseiny, Ghassem Jaberipur:
Complex exponential functions: A high-precision hardware realization. Integr. 73: 18-29 (2020) - [j37]Sina Bakhtavari Mamaghani, Mohammad Hossein Moaiyeri
, Ghassem Jaberipur:
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ. Microelectron. J. 103: 104864 (2020) - [j36]Ghassem Jaberipur
, Bardia Nadimi
:
Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1368-1377 (2020)
2010 – 2019
- 2019
- [j35]Ghassem Jaberipur, Armin Belghadr
, Saeed Nejati:
Impact of diminished-1 encoding on residue number systems arithmetic units and converters. Comput. Electr. Eng. 75: 61-76 (2019) - [c9]Ghassem Jaberipur, Sahar Moradi Cherati
:
Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues. ARITH 2019: 135-142 - 2018
- [j34]Dariush Abedi, Ghassem Jaberipur
:
Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 65-II(1): 106-110 (2018) - [j33]Armin Belghadr
, Ghassem Jaberipur
:
FIR Filter Realization via Deferred End-Around Carry Modular Addition. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2878-2888 (2018) - [j32]Saba Amanollahi, Ghassem Jaberipur:
Extended Redundant-Digit Instruction Set for Energy-Efficient Processors. ACM Trans. Embed. Comput. Syst. 17(3): 70:1-70:21 (2018) - [j31]Ghassem Jaberipur
, Behrooz Parhami, Dariush Abedi:
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies. IEEE Trans. Sustain. Comput. 3(4): 262-273 (2018) - 2017
- [j30]Ghassem Jaberipur, Armin Belghadr:
(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling. Comput. Electr. Eng. 61: 95-103 (2017) - [j29]Saba Amanollahi, Ghassem Jaberipur
:
Fast Energy Efficient Radix-16 Sequential Multiplier. IEEE Embed. Syst. Lett. 9(3): 73-76 (2017) - [j28]Milad Sangsefidi, Dariush Abedi, Ghassem Jaberipur:
Radix-8 full adder in QCA with single clock-zone carry propagation delay. Microprocess. Microsystems 51: 176-184 (2017) - [j27]Saeid Gorgin
, Ghassem Jaberipur
:
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 75-86 (2017) - [j26]Saba Amanollahi, Ghassem Jaberipur
:
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 954-961 (2017) - 2016
- [j25]Morteza Dorrigiv
, Ghassem Jaberipur:
Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding. Comput. Electr. Eng. 50: 39-53 (2016) - [j24]Adel Hosseiny, Ghassem Jaberipur:
Decimal Goldschmidt: A hardware algorithm for radix-10 division. Comput. Electr. Eng. 53: 40-55 (2016) - [j23]Adel Hosseiny, Ghassem Jaberipur:
Decimal Square Root: Algorithm and Hardware Implementation. Circuits Syst. Signal Process. 35(12): 4195-4219 (2016) - [j22]Zeinab Torabi
, Ghassem Jaberipur:
Fast low energy RNS comparators for 4-moduli sets {2n±1, 2n, m} with m∈{2n+1±1, 2n-1-1}. Integr. 55: 155-161 (2016) - [j21]Zeinab Torabi
, Ghassem Jaberipur:
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1849-1857 (2016) - [c8]Ghassem Jaberipur, Behrooz Parhami, Dariush Abedi:
A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements. ARITH 2016: 8-15 - 2015
- [j20]HamidReza Ahmadifar
, Ghassem Jaberipur:
A New Residue Number System with 5-Moduli Set: {22q, 2q±3, 2q±1}. Comput. J. 58(7): 1548-1565 (2015) - [j19]Saeid Gorgin
, Ghassem Jaberipur:
Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings". IEEE Trans. Computers 64(1): 293-294 (2015) - [j18]Ghassem Jaberipur, Seyed Hamed Fatemi Langroudi:
(4+2 log n)ΔG Parallel Prefix Modulo-(2n-3) Adder via Double Representation of Residues in [0, 2]. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 583-587 (2015) - [c7]Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur:
Modulo-(2n - 2q - 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues. ARITH 2015: 121-128 - 2014
- [j17]Saeid Gorgin
, Ghassem Jaberipur, Reza Hashemi Asl:
Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers. Circuits Syst. Signal Process. 33(12): 3883-3899 (2014) - [j16]Ghassem Jaberipur, HamidReza Ahmadifar
:
A ROM-less reverse RNS converter for moduli set {2q±1, 2q±3}. IET Comput. Digit. Tech. 8(1): 11-22 (2014) - [j15]Morteza Dorrigiv
, Ghassem Jaberipur:
Low area/power decimal addition with carry-select correction and carry-select sum-digits. Integr. 47(4): 443-451 (2014) - [c6]Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur:
Double {0, 1, 2} representation modulo-(2n - 3) adders. IWSSIP 2014: 119-122 - 2012
- [j14]Abdoreza Pishvaie, Ghassem Jaberipur, Ali Jahanian
:
Improved CMOS (4; 2) compressor designs for parallel multipliers. Comput. Electr. Eng. 38(6): 1703-1716 (2012) - [j13]Ghassem Jaberipur, Behrooz Parhami:
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits. IET Comput. Digit. Tech. 6(5): 259-268 (2012) - 2011
- [j12]Amir Kaivani, Ghassem Jaberipur:
Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture. Comput. J. 54(11): 1798-1809 (2011) - [j11]Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur:
Improving the speed of decimal division. IET Comput. Digit. Tech. 5(5): 393-404 (2011) - [c5]Ghassem Jaberipur, Behrooz Parhami, Saeed Nejati:
On building general modular adders from standard binary arithmetic components. ACSCC 2011: 154-159 - [c4]Saeid Gorgin
, Ghassem Jaberipur:
A Family of High Radix Signed Digit Adders. IEEE Symposium on Computer Arithmetic 2011: 112-120 - 2010
- [j10]Ghassem Jaberipur, Saeid Gorgin
:
An improved maximally redundant signed digit adder. Comput. Electr. Eng. 36(3): 491-502 (2010) - [j9]Amir Kaivani, Ghassem Jaberipur:
Fully redundant decimal addition and subtraction using stored-unibit encoding. Integr. 43(1): 34-41 (2010) - [j8]Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin
:
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. IEEE Trans. Computers 59(5): 694-706 (2010)
2000 – 2009
- 2009
- [j7]Saeid Gorgin
, Ghassem Jaberipur:
A fully redundant decimal adder and its application in parallel decimal multipliers. Microelectron. J. 40(10): 1471-1481 (2009) - [j6]Ghassem Jaberipur, Amir Kaivani:
Improving the Speed of Parallel Decimal Multiplication. IEEE Trans. Computers 58(11): 1539-1552 (2009) - [c3]Ghassem Jaberipur, Behrooz Parhami:
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues. IEEE Symposium on Computer Arithmetic 2009: 57-64 - [c2]Saeid Gorgin
, Ghassem Jaberipur:
Fully Redundant Decimal Arithmetic. IEEE Symposium on Computer Arithmetic 2009: 145-152 - 2008
- [j5]Ghassem Jaberipur, Behrooz Parhami:
Constant-time addition with hybrid-redundant numbers: Theory and implementations. Integr. 41(1): 49-64 (2008) - [c1]Ghassem Jaberipur, Saeid Gorgin
:
A Nonspeculative Maximally Redundant Signed Digit Adder. CSICC 2008: 235-242 - 2007
- [j4]Ghassem Jaberipur, Behrooz Parhami:
Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic. IET Circuits Devices Syst. 1(1): 102-110 (2007) - [j3]Ghassem Jaberipur, Amir Kaivani:
Binary-coded decimal digit multipliers. IET Comput. Digit. Tech. 1(4): 377-381 (2007) - 2006
- [j2]Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi:
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. J. VLSI Signal Process. 42(2): 149-158 (2006) - 2005
- [j1]Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi:
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(7): 1348-1357 (2005)
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last updated on 2024-08-03 20:13 CEST by the dblp team
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