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ORCIDThomas W. Williams
Person information
- affiliation: Synopsys, Inc., Boulder, CO, USA
- affiliation (former): IBM, Boulder, CO, USA
- affiliation (PhD): Colorado State University, Boulder, CO, USA
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2000 – 2009
- 2008
[j23]Rohit Kapur, Subhasish Mitra
, Thomas W. Williams:
Historical Perspective on Scan Compression. IEEE Des. Test Comput. 25(2): 114-120 (2008)- [c52]J. S. Hobbs, Thomas W. Williams:
Reaching the limits of low power design. ASP-DAC 2008: 732-735 - [c51]Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams:
Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS 2008: 13-18 - [c50]Thomas W. Williams:
The Future Is Low Power and Test. ETS 2008: 4 - [c49]Thomas W. Williams:
EDA to the Rescue of the Silicon Roadmap. ISMVL 2008: 1 - 2007
- [j22]Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri:
DFT MAX and Power. J. Low Power Electron. 3(2): 199-205 (2007) - [c48]Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams:
Accurately Determining Bridging Defects from Layout. DDECS 2007: 87-90 - [c47]Thomas W. Williams:
EDA to the Rescue of the Silicon Roadmap. ISQED 2007: 115-118 - [c46]Rohit Kapur, Jindrich Zejda, Thomas W. Williams:
Fundamentals of timing information for test: How simple can we get? ITC 2007: 1-7 - [c45]Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini:
Minimizing the Impact of Scan Compression. VTS 2007: 67-74 - 2005
- [j21]Thomas W. Williams:
TTTC recognizes test visionary's lifetime contribution. IEEE Des. Test Comput. 22(3): 282, 285 (2005) - [c44]Thomas W. Williams:
Design for Testability: The Path to Deep Submicron. Asian Test Symposium 2005 - [c43]Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur:
Efficient compression of deterministic patterns into multiple PRPG seeds. ITC 2005: 10 - 2004
- [c42]Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams:
Changing the Scan Enable during Shift. VTS 2004: 73-78 - 2003
- [c41]Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch:
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE 2003: 10110-10115 - [c40]Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050 - [c39]Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams:
A Reconfigurable Shared Scan-in Architecture. VTS 2003: 9-14 - 2002
- [j20]Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams:
Dynamic Scan: Driving Down the Cost of Test. Computer 35(10): 63-68 (2002) - [c38]Rohit Kapur, Thomas W. Williams:
Manufacturing Test of SoCs. Asian Test Symposium 2002: 317-319 - [c37]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374 - [c36]Rohit Kapur, Thomas W. Williams, M. Ray Mercer:
Directed-Binary Search in Logic BIST Diagnostics. DATE 2002: 1121 - [c35]Nahmsuk Oh, Rohit Kapur, Thomas W. Williams:
Fast seed computation for reseeding shift register in test pattern compression. ICCAD 2002: 76-81 - [c34]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416 - 2001
- [j19]Rohit Kapur, R. Chandramouli, Thomas W. Williams:
Strategies for Low-Cost Test. IEEE Des. Test Comput. 18(6): 47-54 (2001) - [c33]Peter Wohl, John A. Waicukauski, Thomas W. Williams:
Design of compactors for signature-analyzers in built-in self-test. ITC 2001: 54-63 - [c32]Rohit Kapur, Thomas W. Williams:
Tester retargetable patterns. ITC 2001: 721-727 - [c31]Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir:
A new methodology for improved tester utilization. ITC 2001: 916-923 - 2000
- [j18]Rohit Kapur, Cy Hay, Thomas W. Williams:
The Mutating Metric for Benchmarking Test. IEEE Des. Test Comput. 17(3): 18-21 (2000) - [j17]Don MacMillen, Raul Camposano, Dwight D. Hill, Thomas W. Williams:
An industrial view of electronic design automation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1428-1448 (2000) - [c30]Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu:
DFT closure. Asian Test Symposium 2000: 8-9 - [c29]Thomas W. Williams, Rohit Kapur:
Design for Testability in Nanometer Technologies; Searching for Quality. ISQED 2000: 167-172 - [c28]Thomas W. Williams, Stephen K. Sunter:
How Should Fault Coverage Be Defined? VTS 2000: 325-328
1990 – 1999
- 1999
- [j16]Thomas W. Williams:
IEEE-USA and the Issue of Member Choice. Computer 32(2): 123-124 (1999) - [j15]Rohit Kapur, Thomas W. Williams:
Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. Computer 32(11): 42-45 (1999) - [c27]Thomas W. Williams:
Testing in Nanometer Technologies. DATE 1999: 5- - 1998
- [c26]Thomas W. Williams:
The New Frontier for Testing: Nano Meter Technologies. Asian Test Symposium 1998: 2- - 1996
- [j14]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 1020-1025 (1996) - [j13]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams:
Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1286-1293 (1996) - [c25]Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly:
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC 1996: 578-583 - [c24]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
A Better ATPG Algorithm and Its Design Principles. ICCD 1996: 248-253 - [c23]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
Using Target Faults To Detect Non-Tartget Defects. ITC 1996: 629-638 - [c22]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792 - 1995
- [c21]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
Enhanced testing performance via unbiased test sets. ED&TC 1995: 294-302 - [c20]Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
On Efficiently and Reliably Achieving Low Defective Part Levels. ITC 1995: 616-625 - [c19]Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams:
On the decline of testing efficiency as fault coverage approaches 100%. VTS 1995: 74-83 - 1994
- [c18]José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams:
Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC 1994: 436-442 - [c17]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
Design of an Efficient Weighted-Random-Pattern Generation System. ITC 1994: 491-500 - [c16]Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams:
Limitations in predicting defect level based on stuck-at fault coverage. VTS 1994: 186-191 - 1993
- [c15]Thomas W. Williams:
Design for Testability: Today and in the Future. ICCD 1993: 14 - 1992
- [j12]Eun Sei Park, M. Ray Mercer, Thomas W. Williams:
The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41(6): 688-698 (1992) - 1991
- [j11]André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams:
Iterative algorithms for computing aliasing probabilities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(2): 260-265 (1991) - [c14]Thomas W. Williams, Bill Underwood, M. Ray Mercer:
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC 1991: 87-92 - [c13]Kenneth D. Wagner, Thomas W. Williams:
Enhancing Board Functional Self-Test by Concurrent Sampling. ITC 1991: 633-640 - [c12]Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer:
Delay Testing Quality in Timing-Optimized Designs. ITC 1991: 897-905
1980 – 1989
- 1989
- [j10]Eun Sei Park, M. Ray Mercer, Thomas W. Williams:
A statistical model for delay-fault testing. IEEE Des. Test 6(1): 45-55 (1989) - [c11]Thomas W. Williams:
Future Trends in the Testing. IFIP Congress 1989: 1019-1020 - 1988
- [j9]Larry Carter, Leendert M. Huisman, Tom W. Williams:
TRIM: testability range by ignoring the memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 38-49 (1988) - [j8]Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
Bounds and analysis of aliasing errors in linear feedback shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 75-83 (1988) - [c10]Eun Sei Park, Thomas W. Williams, M. Ray Mercer:
Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC 1988: 492-499 - [c9]Kenneth D. Wagner, Thomas W. Williams:
Design for Testability of Mixed Signal Integrated Circuits. ITC 1988: 823-828 - 1987
- [j7]Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
Aliasing Errors in Signature Analysis Registers. IEEE Des. Test 4(2): 39-45 (1987) - 1986
- [j6]Thomas W. Williams:
Design of testable logic circuits. Proc. IEEE 74(3): 525 (1986) - [c8]Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials. ITC 1986: 282-289 - [c7]Leendert M. Huisman, Larry Carter, Tom W. Williams:
TRIM : Testability Range by Ignoring the Memory. ITC 1986: 474-479 - 1985
- [j5]Thomas W. Williams:
Test Length in a Self-Testing Environment. IEEE Des. Test 2(2): 59-63 (1985) - 1984
- [j4]Thomas W. Williams:
VLSI Testing. Computer 17(10): 126-136 (1984) - [c6]Subrata Dasgupta, M. C. Graf, Robert A. Rasmussen, Ron G. Walther, Tom W. Williams:
Chip partitioning aid: A design technique for partitionability and testability in VLSI. DAC 1984: 203-208 - [c5]Tom W. Williams:
Sufficient Testing In A Self-Testing Environment. ITC 1984: 167-173 - 1982
- [j3]Thomas W. Williams, Kenneth P. Parker:
Design for Testability - A Survey. IEEE Trans. Computers 31(1): 2-15 (1982) - [c4]Thomas W. Williams:
Design for testability. DAC 1982: 9 - [c3]Sumit DasGupta, Prabhakar Goel, Ron G. Walther, Tom W. Williams:
A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI. ITC 1982: 63-66 - [c2]Eugen I. Muehldorf, Thomas W. Williams:
Analysis of the Switching Behavior of Combinatorial Logic Networks. ITC 1982: 379-390
1970 – 1979
- 1979
- [j2]Thomas W. Williams, Kenneth P. Parker:
Testing Logic Networks and Designing for Testability. Computer 12(10): 9-21 (1979) - 1977
- [c1]Edward B. Eichelberger, Thomas W. Williams:
A logic design structure for LSI testability. DAC 1977: 462-468 - 1972
- [j1]Daniel J. Krause, John W. Steadman, Thomas W. Williams:
Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate. IEEE Trans. Syst. Man Cybern. 2(2): 255-261 (1972)
Coauthor Index
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last updated on 2024-06-16 23:47 CEST by the dblp team
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