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ORCIDErik Jan Marinissen
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2020 – today
- 2024
[j50]Zhan Gao
, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology. IEEE Des. Test 41(2): 56-64 (2024)- [c126]Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen:
Silent Data Corruption: Test or Reliability Problem? ETS 2024: 1-7 - [c125]Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra:
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. ETS 2024: 1-10 - [c124]Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen:
Test and Repair Improvements for UCIe. ETS 2024: 1-6 - [c123]Sicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui:
Design-for-Test for Intermittent Faults in STT-MRAMs. ETS 2024: 1-6 - [c122]Dishant Sangani, Ben Kaczer, Pieter Weckx, Philippe J. Roussel, Subrat Mishra, Erik Jan Marinissen, Georges G. E. Gielen:
Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers. IRPS 2024: 1-7 - [c121]Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim:
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair. VTS 2024: 1-11 - 2023
- [c120]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6 - [c119]Ahmed Aouichi, Sicong Yuan, Moritz Fieback, Siddharth Rao, Woojin Kim, Erik Jan Marinissen, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui:
Device Aware Diagnosis for Unique Defects in STT-MRAMs. ATS 2023: 1-6 - [c118]Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Said Hamdioui:
Device-Aware Test for Back-Hopping Defects in STT-MRAMs. DATE 2023: 1-6 - [c117]Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen:
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS 2023: 1-6 - [c116]Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen:
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC 2023: 151-158 - [c115]Sicong Yuan, Z. Zhang, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui:
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. ITC 2023: 236-245 - [c114]Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen:
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. ITC-Asia 2023: 1-6 - [c113]Erik Jan Marinissen:
Moore Meets Murphy : Invited Talk 1. ITC-Asia 2023: 1 - [c112]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - [c111]Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty:
IP Session on Chiplet: Design, Assembly, and Test. VTS 2023: 1 - 2022
- [j49]Adam Cron, Hailong Jiao, Erik Jan Marinissen:
Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages. IEEE Des. Test 39(5): 5-6 (2022) - [j48]Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen:
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test 39(5): 79-87 (2022) - [j47]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. IEEE Trans. Computers 71(9): 2219-2233 (2022) - [j46]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4991-5004 (2022) - [j45]Xugang Cao, Hailong Jiao, Erik Jan Marinissen:
A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 554-558 (2022) - 2021
- [j44]Adam Cron, Erik Jan Marinissen:
IEEE Standard 1838 Is on the Move. Computer 54(11): 88-94 (2021) - [j43]Yu-Rong Jian, Ferenc Fodor, Cheng-Wen Wu, Erik Jan Marinissen:
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization. IEEE Des. Test 38(5): 82-89 (2021) - [j42]Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality. J. Electron. Test. 37(2): 161-189 (2021) - [j41]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Guilherme Cardoso Medeiros, Moritz Fieback, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Defect and Fault Modeling Framework for STT-MRAM Testing. IEEE Trans. Emerg. Top. Comput. 9(2): 707-723 (2021) - [c110]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. DATE 2021: 1717-1722 - [c109]Francesco Lorenzelli, Zhan Gao, Joe Swenton, Santosh Malagi, Erik Jan Marinissen:
Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. ETS 2021: 1-6 - [c108]Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen:
Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. ETS 2021: 1-4 - [c107]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. ITC 2021: 143-152 - 2020
- [c106]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Impact of Magnetic Coupling and Density on STT-MRAM Performance. DATE 2020: 1211-1216 - [c105]Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen:
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS 2020: 1-6 - [c104]Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen:
Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. ETS 2020: 1-6 - [c103]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. ITC 2020: 1-10 - [i3]Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui:
Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. CoRR abs/2001.05463 (2020) - [i2]Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Impact of Magnetic Coupling and Density on STT-MRAM Performance. CoRR abs/2011.11349 (2020)
2010 – 2019
- 2019
- [c102]Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne:
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC 2019: 1-6 - [c101]Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar:
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. ETS 2019: 1-6 - [c100]Moritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui:
Device-Aware Test: A New Test Approach Towards DPPB Level. ITC 2019: 1-10 - [c99]Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen:
Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library. ITC 2019: 1-6 - [c98]Zhan Gao, Min-Chun Hu, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices. ITC-Asia 2019: 91-96 - [c97]Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens:
Defect-Location Identification for Cell-Aware Test. LATS 2019: 1-6 - 2018
- [c96]Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen:
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. ETS 2018: 1-6 - [c95]Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen:
Automatic generation of in-circuit tests for board assembly defects. ETS 2018: 1-2 - [c94]Leonidas Katselas, Alkis A. Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen:
On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. ITC 2018: 1-9 - [c93]Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu:
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC 2018: 1-10 - [c92]Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui:
Electrical Modeling of STT-MRAM Defects. ITC 2018: 1-10 - [c91]Harm van Schaaijk, Martien Spierings, Erik Jan Marinissen:
Automatic Generation of In-Circuit Tests for Board Assembly Defects. ITC-Asia 2018: 13-18 - 2017
- [j40]Erik Jan Marinissen, Yervant Zorian:
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory. IEEE Des. Test 34(1): 6-7 (2017) - [c90]Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Jorg Kiesewetter, Eric Hill, Ken Smith:
A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards. ITC-Asia 2017: 144-149 - [c89]Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis, Christos Papameletis, Alkis A. Hatzopoulos, Erik Jan Marinissen:
Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. PATMOS 2017: 1-8 - 2016
- [j39]S. Saqib Khursheed, Pascal Vivet, Fabian Hopsch, Erik Jan Marinissen:
Guest Editors' Introduction: Robust 3-D Stacked ICs. IEEE Des. Test 33(3): 6-7 (2016) - [c88]Jeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen, Philippe Absil, Joris Van Campenhout, Bryan Bolt:
Test-station for flexible semi-automatic wafer-level silicon photonics testing. ETS 2016: 1-6 - [c87]Erik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao:
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. ETS 2016: 1-10 - [c86]Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes:
IoT: Source of test challenges. ETS 2016: 1-10 - 2015
- [j38]Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen:
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test 32(4): 40-48 (2015) - [j37]Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen:
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. IEEE Trans. Computers 64(12): 3335-3347 (2015) - [j36]Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen:
Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1860-1872 (2015) - [j35]Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen:
Robust Optimization of Test-Access Architectures Under Realistic Scenarios. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1873-1884 (2015) - [j34]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen:
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching. ACM Trans. Design Autom. Electr. Syst. 20(2): 19:1-19:23 (2015) - [c85]Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne:
Processing active devices on Si interposer and impact on cost. 3DIC 2015: TS11.2.1-TS11.2.4 - [c84]Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen:
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS 2015: 79-84 - [c83]Erik Jan Marinissen, Bart De Wachter, Teng Wang, Jens Fiedler, Jorg Kiesewetter, Karsten Stoll:
Automated testing of bare die-to-die stacks. ITC 2015: 1-10 - [c82]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean:
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2014
- [j33]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2388-2401 (2014) - [c81]Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen:
Interconnect test for 3D stacked memory-on-logic. DATE 2014: 1-6 - [c80]Erik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr:
Vesuvius-3D: A 3D-DfT demonstrator. ITC 2014: 1-10 - [c79]Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui:
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface. ITC 2014: 1-10 - [c78]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen:
Quality versus cost analysis for 3D Stacked ICs. VTS 2014: 1-6 - 2013
- [c77]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik:
Using 3D-COSTAR for 2.5D test cost optimization. 3DIC 2013: 1-8 - [c76]Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne:
Si interposer build-up options and impact on 3D system cost. 3DIC 2013: 1-5 - [c75]Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne:
Design issues in heterogeneous 3D/2.5D integration. ASP-DAC 2013: 403-410 - [c74]Erik Jan Marinissen:
Creating options for 3D-SIC testing. DDECS 2013: 7 - [c73]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik:
Impact of mid-bond testing in 3D stacked ICs. DFTS 2013: 178-183 - [c72]Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui:
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS 2013: 1-6 - [c71]Erik Jan Marinissen:
Murphy goes 3D. ISVLSI 2013: 102 - [c70]Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen:
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs. ITC 2013: 1-10 - [c69]Erik Jan Marinissen:
Creating options for 3D-SIC testing. VLSI-DAT 2013: 1-7 - 2012
- [j32]Erik Jan Marinissen:
Pioneering in Asia With the US Venture Capital Model. IEEE Des. Test Comput. 29(6): 52-55 (2012) - [j31]Erik Jan Marinissen, Yervant Zorian:
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electron. Test. 28(1): 13-14 (2012) - [j30]Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen:
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost. J. Electron. Test. 28(1): 15-25 (2012) - [j29]Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg, Jouke Verbree:
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. J. Electron. Test. 28(1): 73-92 (2012) - [j28]Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen:
Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J. Electron. Test. 28(1): 103-120 (2012) - [c68]Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl:
EDA solutions to new-defect detection in advanced process technologies. DATE 2012: 123-128 - [c67]Erik Jan Marinissen:
Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs. DATE 2012: 1277-1282 - [c66]Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10 - 2011
- [j27]Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree:
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1705-1718 (2011) - [c65]Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel:
Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400 - [c64]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456 - [c63]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
DfT Architecture for 3D-SICs with Multiple Towers. ETS 2011: 51-56 - [c62]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen:
On modeling and optimizing cost in 3D Stacked-ICs. IDT 2011: 24-29 - [c61]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10 - [c60]Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel:
Evaluation of TSV and micro-bump probing for wide I/O testing. ITC 2011: 1-10 - [p1]Erik Jan Marinissen:
Testing 3D Stacked ICs Containing Through-Silicon Vias. 3D Integration for NoC-based SoC Architectures 2011: 47-74 - 2010
- [j26]Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens:
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism. J. Electron. Test. 26(4): 453-464 (2010) - [c59]Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario Konijnenburg:
3D DfT architecture for pre-bond and post-bond testing. 3DIC 2010: 1-8 - [c58]Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne:
Cost effectiveness of 3D integration options. 3DIC 2010: 1-6 - [c57]Erik Jan Marinissen:
Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access. APCCAS 2010: 544-547 - [c56]Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen:
Test Cost Analysis for 3D Die-to-Wafer Stacking. Asian Test Symposium 2010: 435-441 - [c55]Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli:
Adapting to adaptive testing. DATE 2010: 556-561 - [c54]Erik Jan Marinissen:
Testing TSV-based three-dimensional stacked ICs. DATE 2010: 1689-1694 - [c53]Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree:
Test-architecture optimization for TSV-based 3D stacked ICs. ETS 2010: 24-29 - [c52]Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis:
On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. ETS 2010: 36-41 - [c51]Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal:
3D integration: Circuit design, test, and reliability challenges. IOLTS 2010: 217 - [c50]Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen:
On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. ITC 2010: 183-192 - [c49]Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen:
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. ITC 2010: 193-201 - [c48]Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg:
A structured and scalable test access architecture for TSV-based 3D stacked ICs. VTS 2010: 269-274
2000 – 2009
- 2009
- [j25]Erik Jan Marinissen, Yervant Zorian:
Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Des. Test Comput. 26(1): 6-7 (2009) - [j24]Erik Jan Marinissen, Yervant Zorian:
IEEE Std 1500 Enables Modular SoC Testing. IEEE Des. Test Comput. 26(