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ORCIDSebastian Hahn 0001
Person information
- affiliation: Saarland University, Department of Computer Science
Other persons with the same name
- Sebastian Hahn — disambiguation page
- Sebastian Hahn 0002
![[0000-0002-4855-6273]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-4855-6273")
— TU Wien, Department of Geodesy and Geoinformation, Vienna, Austria - Sebastian Hahn 0003 (aka: Sebastian Schmechel) — University of Potsdam, Hasso Plattner Institute
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Books and Theses
- 2019
[b1]Sebastian Hahn:
On static execution-time analysis. Saarland University, Saarbrücken, Germany, 2019
Journal Articles
- 2020
- [j2]Sebastian Hahn, Jan Reineke:
Design and analysis of SIC: a provably timing-predictable pipelined processor core. Real Time Syst. 56(2): 207-245 (2020) - 2015
- [j1]Sebastian Hahn, Jan Reineke, Reinhard Wilhelm:
Towards compositionality in execution time analysis: definition and challenges. SIGBED Rev. 12(1): 28-36 (2015)
Conference and Workshop Papers
- 2024
- [c14]Daniel Kästner, Laurent Mauborgne, Sebastian Hahn, Stephan Wilhelm, Jörg Herter, Christoph Cullmann, Christian Ferdinand:
Sound Non-interference Analysis for C/C++. SAFECOMP 2024: 267-282 - 2022
- [c13]Sebastian Hahn, Michael Jacobs, Nils Hölscher, Kuan-Hsun Chen, Jian-Jia Chen, Jan Reineke:
LLVMTA: An LLVM-Based WCET Analysis Tool. WCET 2022: 2:1-2:17 - 2020
- [c12]Daniel Kästner, Christoph Cullmann, Gernot Gebhard, Sebastian Hahn, Thomas Karos, Laurent Mauborgne, Stephan Wilhelm, Christian Ferdinand:
Safety-Critical Software Development in C++. SAFECOMP Workshops 2020: 98-110 - 2019
- [c11]Gregory Stock, Sebastian Hahn, Jan Reineke:
Cache Persistence Analysis: Finally Exact. RTSS 2019: 481-494 - 2018
- [c10]Sebastian Hahn, Jan Reineke:
Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core. RTSS 2018: 469-481 - [c9]Darshit Shah, Sebastian Hahn, Jan Reineke:
Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis. WCET 2018: 7:1-7:11 - 2017
- [c8]Tobias Blaß, Sebastian Hahn, Jan Reineke:
Write-Back Caches in WCET Analysis. ECRTS 2017: 26:1-26:22 - 2016
- [c7]Michael Jacobs, Sebastian Hahn, Sebastian Hack:
A Framework for the Derivation of WCET Analyses for Multi-core Processors. ECRTS 2016: 141-151 - [c6]Sebastian Hahn, Michael Jacobs, Jan Reineke:
Enabling Compositionality for Multicore Timing Analysis. RTNS 2016: 299-308 - 2015
- [c5]Sebastian Hahn, Jan Reineke, Reinhard Wilhelm:
Toward Compact Abstractions for Processor Pipelines. Correct System Design 2015: 205-220 - [c4]Michael Jacobs, Sebastian Hahn, Sebastian Hack:
WCET analysis for multi-core processors with shared buses and event-driven bus arbitration. RTNS 2015: 193-202 - 2014
- [c3]Jan Reineke, Sebastian Altmeyer, Daniel Grund, Sebastian Hahn, Claire Maiza:
Selfish-LRU: Preemption-aware caching for predictability and performance. RTAS 2014: 135-144 - 2013
- [c2]Andreas Abel, Florian Benz, Johannes Doerfert, Barbara Dörr, Sebastian Hahn, Florian Haupenthal, Michael Jacobs, Amir H. Moin, Jan Reineke, Bernhard Schommer, Reinhard Wilhelm:
Impact of Resource Sharing on Performance and Performance Prediction: A Survey. CONCUR 2013: 25-43 - 2012
- [c1]Sebastian Hahn, Daniel Grund:
Relational Cache Analysis for Static Timing Analysis. ECRTS 2012: 102-111
Informal and Other Publications
- 2019
- [i1]Gregory Stock, Sebastian Hahn, Jan Reineke:
Cache Persistence Analysis: Finally Exact. CoRR abs/1909.04374 (2019)
Coauthor Index
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