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ORCIDSung-Yong Cho
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2020 – today
- 2024
[c10]Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang:
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. ISSCC 2024: 242-244- 2021
- [j10]Kwanseo Park
, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong:
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits 56(5): 1597-1607 (2021) - [j9]Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong:
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021)
2010 – 2019
- 2019
- [j8]Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54(10): 2812-2822 (2019) - [j7]Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim:
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1927-1931 (2019) - [j6]Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong:
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019) - [c9]Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong:
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits 2019: 194- - 2018
- [j5]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong:
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - [j4]Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1819-1823 (2018) - [c8]Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong:
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC 2018: 73-76 - 2017
- [c7]Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong:
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC 2017: 494-495 - 2016
- [j3]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. IEEE J. Solid State Circuits 51(10): 2312-2327 (2016) - [j2]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE J. Solid State Circuits 51(10): 2357-2367 (2016) - [j1]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1393-1403 (2016) - [c6]Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong:
A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS 2016: 1662-1665 - 2015
- [c5]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC 2015: 1-4 - [c4]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC 2015: 1-4 - [c3]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong:
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC 2015: 384-387 - 2014
- [c2]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450
2000 – 2009
- 2004
- [c1]Sung-Yong Cho, Jae-Hong Shim:
A new micro biological cell injection system. IROS 2004: 1642-1647
Coauthor Index
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