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2010 – 2019
- 2019
[c8]Minwook Ahn, Seok Joong Hwang, Wonsub Kim, Seungrok Jung, Yeonbok Lee, Mookyoung Chung, Woohyung Lim, Young Joon Kim:
AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition. DATE 2019: 1495-1500- [c7]Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet
, Laurent Souriau, Shamin H. Sharifi, Johan Swerts, Robert Carpenter, Sidharth Rao, Wonsub Kim, J. Wu, K. K. V. Sethu, M. Pak, N. Jossart, D. Crotti, Arnaud Furnémont, Gouri Sankar Kar:
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. VLSI Circuits 2019: 194- - 2018
- [c6]Barry J. O'Sullivan, Simon Van Beek, Philippe J. Roussel, Sidharth Rao, Wonsub Kim, S. Couet, Johan Swerts, Farrukh Yasin, Dimitri Crotti, Dimitri Linten, Gouri Sankar Kar:
Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown. IRPS 2018: 5-1 - [c5]Jun Hyung Kim, Jazzson Park, Minwook Ahn, Yeonbok Lee, Wonsub Kim, Hyung-Min Park:
Online Speech Dereverberation Using RLS-WPE Based on a Full Spatial Correlation Matrix Integrated in a Speech Enhancement System. IWAENC 2018: 36-40 - [c4]Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, Kris Croes, N. Jossart, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Fumemont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. VLSI Circuits 2018: 81-82 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018) - 2013
- [j1]Wonsub Kim, Yoonseo Choi, Haewoo Park:
Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures. ACM Trans. Archit. Code Optim. 10(4): 58:1-58:24 (2013) - [c3]Haewoo Park, Wonsub Kim, Donghoon Yoo, Soojung Ryu, Jeongwook Kim:
A scalable scheduling algorithm for coarse-grained reconfigurable architecture. ICCE 2013: 542-543 - 2012
- [c2]Wonsub Kim, Donghoon Yoo, Haewoo Park, Minwook Ahn:
SCC based modulo scheduling for coarse-grained reconfigurable processors. FPT 2012: 321-328
2000 – 2009
- 2001
- [c1]Wonsub Kim, Jinsoo Park:
Performance analysis of wideband DS-CDMA cellular system over Nakagami fading channels. VTC Fall 2001: 576-580
Coauthor Index
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