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ORCIDQijing Huang 0001
Person information
- affiliation: NVIDIA Research, Berkeley, CA, USA
- affiliation (former): University of California, Berkeley, CA, USA
- affiliation (former): University of Toronto, ON, Canada
Other persons with the same name
- Qijing Huang 0002 — College of Computer Science and Technology, Shanghai, China
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2020 – today
- 2025
[c24]Arash Ardakani
, Minwoo Kang, Kevin He, Qijing Huang, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek:
DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. ASP-DAC 2025: 1328-1335- [c23]Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek:
High-Throughput SAT Sampling. DATE 2025: 1-7 - [c22]Haoyu Yang, Qijing Huang, Nathaniel Ross Pinckney, Walker J. Turner, Wenfei Zhou, Yanqing Zhang, Chia-Tung Ho, Chen-Chia Chang, Haoxing Ren:
ChipVQA: Benchmarking Visual Language Models for Chip Design. DATE 2025: 1-6 - [c21]Benjamin Kubwimana, Qijing Huang:
EdgeReasoning: Characterizing Reasoning LLM Deployment on Edge GPUs. IISWC 2025: 99-115 - [i15]Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek:
DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. CoRR abs/2502.08086 (2025) - [i14]Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek:
High-Throughput SAT Sampling. CoRR abs/2502.08673 (2025) - [i13]Charles Hong, Qijing Huang, Grace Dinh, Mahesh Subedar, Yakun Sophia Shao:
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators. CoRR abs/2509.10702 (2025) - [i12]Benjamin Kubwimana, Qijing Huang:
EdgeReasoning: Characterizing Reasoning LLM Deployment on Edge GPUs. CoRR abs/2511.01866 (2025) - 2024
- [c20]Qijing Huang, Po-An Tsai, Joel S. Emer, Angshuman Parashar:
Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms. ISCA 2024: 150-166 - 2023
- [c19]Charles Hong, Qijing Huang, Grace Dinh, Mahesh Subedar, Yakun Sophia Shao:
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators. MICRO 2023: 209-224 - [i11]Sehoon Kim, Coleman Hooper, Thanakul Wattanawong, Minwoo Kang, Ruohan Yan, Hasan Genc, Grace Dinh, Qijing Huang, Kurt Keutzer, Michael W. Mahoney, Yakun Sophia Shao, Amir Gholami:
Full Stack Optimization of Transformer Inference: a Survey. CoRR abs/2302.14017 (2023) - 2022
- [c18]Qijing Huang, Charles Hong, John Wawrzynek, Mahesh Subedar, Yakun Sophia Shao:
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. ISPASS 2022: 277-287 - 2021
- [b1]Qijing Huang:
Co-design ofAlgorithms, Hardware, and Scheduling for Deep Learning Applications. University of California, Berkeley, USA, 2021 - [c17]Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer:
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. FCCM 2021: 50-59 - [c16]Qijing Huang, Dequan Wang, Zhen Dong, Yizhao Gao, Yaohui Cai, Tian Li, Bichen Wu, Kurt Keutzer, John Wawrzynek:
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. FPGA 2021: 206-216 - [c15]Zhewei Yao, Zhen Dong, Zhangcheng Zheng, Amir Gholami, Jiali Yu, Eric Tan, Leyuan Wang, Qijing Huang, Yida Wang, Michael W. Mahoney, Kurt Keutzer:
HAWQ-V3: Dyadic Neural Network Quantization. ICML 2021: 11875-11886 - [c14]Qijing Huang, Aravind Kalaiah, Minwoo Kang, James Demmel, Grace Dinh, John Wawrzynek, Thomas Norell, Yakun Sophia Shao:
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. ISCA 2021: 554-566 - [i10]Zhen Dong, Yizhao Gao, Qijing Huang, John Wawrzynek, Hayden K. H. So, Kurt Keutzer:
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference. CoRR abs/2104.12766 (2021) - [i9]Qijing Huang, Minwoo Kang, Grace Dinh, Thomas Norell, Aravind Kalaiah, James Demmel, John Wawrzynek, Yakun Sophia Shao:
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. CoRR abs/2105.01898 (2021) - 2020
- [c13]Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic:
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs. DATE 2020: 490-495 - [c12]Ameer Haj-Ali, Qijing (Jenny) Huang, William S. Moses, John Xiang, Krste Asanovic, John Wawrzynek, Ion Stoica:
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. MLSys 2020 - [c11]Farzad Farshchi, Qijing Huang, Heechul Yun:
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. RTAS 2020: 364-375 - [i8]Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek:
Algorithm-hardware Co-design for Deformable Convolution. CoRR abs/2002.08357 (2020) - [i7]Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. CoRR abs/2003.00671 (2020) - [i6]Ameer Haj-Ali, Hasan Genc, Qijing Huang, William S. Moses, John Wawrzynek, Krste Asanovic, Ion Stoica:
ProTuner: Tuning Programs with Monte Carlo Tree Search. CoRR abs/2005.13685 (2020) - [i5]Zhen Dong, Dequan Wang, Qijing Huang, Yizhao Gao, Yaohui Cai, Bichen Wu, Kurt Keutzer, John Wawrzynek:
CoDeNet: Algorithm-hardware Co-design for Deformable Convolution. CoRR abs/2006.08357 (2020) - [i4]Zhewei Yao, Zhen Dong, Zhangcheng Zheng, Amir Gholami, Jiali Yu, Eric Tan, Leyuan Wang, Qijing Huang, Yida Wang, Michael W. Mahoney, Kurt Keutzer:
HAWQV3: Dyadic Neural Network Quantization. CoRR abs/2011.10680 (2020)
2010 – 2019
- 2019
- [j2]Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Howard Katz, Jonathan Bachrach, Krste Asanovic:
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. IEEE Micro 39(3): 56-65 (2019) - [c10]Farzad Farshchi, Qijing Huang, Heechul Yun:
Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim. EMC2@HPCA/CVPR/ISCA 2019: 21-25 - [c9]Qijing Huang, Ameer Haj-Ali, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. FCCM 2019: 308 - [c8]Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. FPGA 2019: 23-32 - [c7]Lisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanovic, David A. Patterson, Anthony D. Joseph:
FPGA Accelerated INDEL Realignment in the Cloud. HPCA 2019: 277-290 - [c6]Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanovic, John Wawrzynek:
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. ICCAD 2019: 1-8 - [c5]Qijing Huang, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, John Wawrzynek:
Algorithm-hardware Co-design for Deformable Convolution. EMC2@NeurIPS 2019: 48-51 - [i3]Ameer Haj Ali, Qijing Huang, William S. Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek:
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. CoRR abs/1901.04615 (2019) - [i2]Farzad Farshchi, Qijing Huang, Heechul Yun:
Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim. CoRR abs/1903.06495 (2019) - 2018
- [c4]Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy H. Katz, Jonathan Bachrach, Krste Asanovic:
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. ISCA 2018: 29-42 - [i1]Yifan Yang, Qijing Huang, Bichen Wu, Tianjun Zhang, Liang Ma, Giulio Gambardella, Michaela Blott, Luciano Lavagno, Kees A. Vissers, John Wawrzynek, Kurt Keutzer:
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. CoRR abs/1811.08634 (2018) - 2017
- [c3]Shaoyi Cheng, Qijing Huang, John Wawrzynek:
Synthesis of program binaries into FPGA accelerators with runtime dependence validation. FPT 2017: 96-103 - 2015
- [j1]Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Brown, Jason Helge Anderson:
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3): 14:1-14:26 (2015) - 2013
- [c2]Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson:
From software to accelerators with LegUp high-level synthesis. CASES 2013: 18:1-18:9 - [c1]Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Brown, Jason Helge Anderson:
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. FCCM 2013: 89-96
Coauthor Index
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