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ORCIDShubham Jain 0004
Person information
- affiliation: IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
- affiliation (PhD): Purdue University, West Lafayette, IN, USA
Other persons with the same name
- Shubham Jain — disambiguation page
- Shubham Jain 0001
![[0000-0001-5892-7085]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0001-5892-7085")
— Norwegian University of Science and Technology, Trondheim, Norway - Shubham Jain 0002 — IIT Guwahati, India
- Shubham Jain 0003 — Stony Brook University, NY, USA
- Shubham Jain 0005 — Nvidia Corporation, Santa Clara, CA, USA
- Shubham Jain 0006 — Sense Street, London, UK (and 1 more)
- Shubham Jain 0007 — Hughes Systique, Gurugram, India
- Shubham Jain 0008 — Indian Institute of Technology Bombay, Mumbai, India
- Shubham Jain 0009 — Indian Institute of Technology Hyderabad, India
- Shubham Jain 0010 — Technological University of the Shannon, Athlone, Ireland (and 1 more)
- Shubham Jain 0011 — Visa Research, Palo Alto, CA, USA
- Shubham Jain 0012 — Meesho
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2020 – today
- 2025
[j14]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. IEEE J. Solid State Circuits 60(1): 49-64 (2025)- [j13]William Andrew Simon, Irem Boybat, Riselda Kodra, Elena Ferro, Gagandeep Singh, Mohammed Alser, Shubham Jain, Hsinyu Tsai, Geoffrey W. Burr, Onur Mutlu, Abu Sebastian:
CiMBA: Accelerating Genome Sequencing Through On-Device Basecalling via Compute-in-Memory. IEEE Trans. Parallel Distributed Syst. 36(6): 1130-1145 (2025) - [i8]William Andrew Simon, Irem Boybat, Riselda Kodra, Elena Ferro, Gagandeep Singh, Mohammed Alser, Shubham Jain, Hsinyu Tsai, Geoffrey W. Burr, Onur Mutlu, Abu Sebastian:
CiMBA: Accelerating Genome Sequencing through On-Device Basecalling via Compute-in-Memory. CoRR abs/2504.07298 (2025) - 2024
- [j12]Sanchari Sen, Shubham Jain, Sarada Krithivasan, Swagath Venkataramani, Vijayalakshmi Srinivasan:
DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU. IEEE Micro 44(6): 63-72 (2024) - [c13]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang:
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256 - 2023
- [j11]Shubham Jain, Hsinyu Tsai, Ching-Tzu Chen, Ramachandran Muralidhar, Irem Boybat, Martin M. Frank, Stanislaw Wozniak, Milos Stanisavljevic, Praneet Adusumilli, Pritish Narayanan, Kohji Hosokawa, Masatoshi Ishii, Arvind Kumar, Vijay Narayanan, Geoffrey W. Burr:
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 114-127 (2023) - [c12]Martin M. Frank, Ning Li, Malte J. Rasch, Shubham Jain, Ching-Tzu Chen, Ramachandran Muralidhar, Jin-Ping Han, Vijay Narayanan, Timothy Philip, Kevin Brew, Andrew Simon, Iqbal Saraf, Nicole Saulnier, Irem Boybat, Stanislaw Wozniak, Abu Sebastian, Pritish Narayanan, Charles Mackin, An Chen, Hsinyu Tsai, Geoffrey W. Burr:
Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited). IRPS 2023: 1-10 - [c11]Hsinyu Tsai, Pritish Narayanan, Shubham Jain, Stefano Ambrogio, Kohji Hosokawa, Masatoshi Ishii, Charles Mackin, Ching-Tzu Chen, Atsuya Okazaki, Akiyo Nomura, Irem Boybat, Ramachandran Muralidhar, Martin M. Frank, Takeo Yasuda, Alexander M. Friz, Yasuteru Kohda, An Chen, Andrea Fasoli, Malte J. Rasch, Stanislaw Wozniak, Jose Luquin, Vijay Narayanan, Geoffrey W. Burr:
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). ISCAS 2023: 1-5 - 2022
- [j10]Reena Elangovan, Shubham Jain, Anand Raghunathan:
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration. ACM Trans. Design Autom. Electr. Syst. 27(3): 28:1-28:20 (2022) - 2021
- [j9]Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan:
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 326-338 (2021) - [j8]Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan:
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 730-738 (2021) - [c10]Indranil Chakraborty, Sourjya Roy, Shrihari Sridharan, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Anand Raghunathan:
Design Tools for Resistive Crossbar based Machine Learning Accelerators. AICAS 2021: 1-4 - [c9]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan:
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - 2020
- [j7]Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan:
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108(12): 2232-2250 (2020) - [j6]Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Sourjya Roy, Shrihari Sridharan, Amogh Agrawal, Anand Raghunathan, Kaushik Roy:
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges. Proc. IEEE 108(12): 2276-2310 (2020) - [j5]Shubham Jain, Anand Raghunathan:
CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems. ACM Trans. Embed. Comput. Syst. 18(6): 113:1-113:23 (2020) - [j4]Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1567-1577 (2020) - [c8]Sandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks. DATE 2020: 31-36 - [c7]David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, Xiaobo Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael T. Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin:
Emerging Neural Workloads and Their Impact on Hardware. DATE 2020: 1462-1471 - [i7]Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan:
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems. CoRR abs/2002.11151 (2020) - [i6]Reena Elangovan, Shubham Jain, Anand Raghunathan:
Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration. CoRR abs/2011.13000 (2020)
2010 – 2019
- 2019
- [j3]Shubham Jain, Aayush Ankit, Indranil Chakraborty, Tayfun Gokmen, Malte J. Rasch, Wilfried Haensch, Kaushik Roy, Anand Raghunathan:
Neural network accelerator design with resistive crossbars: Opportunities and challenges. IBM J. Res. Dev. 63(6): 10:1-10:13 (2019) - [j2]Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks. IEEE Trans. Computers 68(6): 912-925 (2019) - [c6]Ashish Ranjan, Shubham Jain, Jacob R. Stevens, Dipankar Das, Bharat Kaul, Anand Raghunathan:
X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks. DAC 2019: 130 - [c5]Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Kailash Gopalakrishnan, Leland Chang:
BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks. DAC 2019: 201 - [c4]Sandeep Krishna Thirumala, Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta:
Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation. ISLPED 2019: 1-6 - [p1]Ashish Ranjan, Swagath Venkataramani, Shubham Jain, Younghoon Kim, Shankar Ganesh Ramasubramanian, Arnab Raha, Kaushik Roy, Anand Raghunathan:
Automatic Synthesis Techniques for Approximate Circuits. Approximate Circuits 2019: 123-140 - [i5]Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
TiM-DNN: Ternary in-Memory accelerator for Deep Neural Networks. CoRR abs/1909.06892 (2019) - [i4]Sandeep Krishna Thirumala, Yi-Tse Hung, Shubham Jain, Arnab Raha, Niharika Thakuria, Vijay Raghunathan, Anand Raghunathan, Zhihong Chen, Sumeet Kumar Gupta:
Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support. CoRR abs/1912.07821 (2019) - 2018
- [j1]Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory With Spin-Transfer Torque Magnetic RAM. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 470-483 (2018) - [c3]Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Pierce Chuang, Leland Chang:
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. DAC 2018: 38:1-38:6 - [c2]Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan:
Computing-in-memory with spintronics. DATE 2018: 1640-1645 - [i3]Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan:
Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars. CoRR abs/1809.00072 (2018) - 2017
- [i2]Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan:
Computing in Memory with Spin-Transfer Torque Magnetic RAM. CoRR abs/1703.02118 (2017) - [i1]Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
SparCE: Sparsity aware General Purpose Core Extensions to Accelerate Deep Neural Networks. CoRR abs/1711.06315 (2017) - 2016
- [c1]Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
Approximation through logic isolation for the design of quality configurable circuits. DATE 2016: 612-617
Coauthor Index
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