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ORCIDRakshith Saligram
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Journal Articles
- 2022
[j1]Rakshith Saligram
, Suman Datta, Arijit Raychowdhury:
Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4610-4618 (2022)
Conference and Workshop Papers
- 2024
- [c10]Rakshith Saligram, Amol D. Gaidhane, Yu Kevin Cao, Suman Datta, Arijit Raychowdhury:
Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories. ISLPED 2024: 1-6 - [c9]Laith A. Shamieh, Wei-Chun Wang, Shida Zhang, Rakshith Saligram, Amol D. Gaidhane, Yu Cao, Arijit Raychowdhury, Suman Datta, Saibal Mukhopadhyay:
Cryogenic Operation of Computing-In-Memory based Spiking Neural Network. ISLPED 2024: 1-6 - 2023
- [c8]Rakshith Saligram, Suman Datta, Arijit Raychowdhury:
Cryogenic CMOS as an Enabler for Low Power Dynamic Logic. ISLPED 2023: 1-6 - 2022
- [c7]Wriddhi Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, Suman Datta:
Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing. VLSI Technology and Circuits 2022: 302-303 - 2021
- [c6]Rakshith Saligram, Suman Datta, Arijit Raychowdhury:
CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications. CICC 2021: 1-2 - [c5]Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline:
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. CICC 2021: 1-2 - 2020
- [c4]Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury:
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. VLSI-SoC (Selected Papers) 2020: 149-178 - [c3]Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury:
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. VLSI-SOC 2020: 159-164 - 2013
- [c2]Rakshith Saligram, T. R. Rakshith:
Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate. ICACCI 2013: 862-867 - [c1]Rakshith Saligram:
Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG. ISED 2013: 46-51
Informal and Other Publications
- 2013
- [i1]Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi, M. K. Venkatesha:
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit. CoRR abs/1307.3690 (2013)
Coauthor Index
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