BibTeX records: Siu Lung Chan

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@article{DBLP:journals/jssc/CerneaPMCLLTTN009,
  author    = {Raul Cernea and
               Long Pham and
               Farookh Moogat and
               Siu Lung Chan and
               Binh Le and
               Yan Li and
               Shouchang Tsao and
               Taiyuan Tseng and
               Khanh Nguyen and
               Jason Li and
               Jayson Hu and
               Jonghak Yuh and
               Cynthia Hsu and
               Fanglin Zhang and
               Teruhiko Kamei and
               Hiroaki Nasu and
               Phil Kliza and
               Khin Htoo and
               Jeffrey Lutze and
               Yingda Dong and
               Masaaki Higashitani and
               Junhui Yang and
               Hung{-}Szu Lin and
               Vamshi Sakhamuri and
               Alan Li and
               Feng Pan and
               Sridhar Yadala and
               Subodh Taigor and
               Kishan Pradhan and
               James Lan and
               Jim Chan and
               Takumi Abe and
               Yasuyuki Fukuda and
               Hideo Mukai and
               Koichi Kawakami and
               Connie Liang and
               Tommy Ip and
               Shu{-}Fen Chang and
               Jaggi Lakshmipathi and
               Sharon Huynh and
               Dimitris Pantelakis and
               Mehrdad Mofidi and
               Khandker Quader},
  title     = {A 34 MB/s {MLC} Write Throughput 16 Gb {NAND} With All Bit Line Architecture
               on 56 nm Technology},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {44},
  number    = {1},
  pages     = {186--194},
  year      = {2009}
}

@inproceedings{DBLP:conf/isscc/CerneaPMCLLTTNLHPHZKNKHLDHYLSLPYTPLCAFMKLICLHPMQ08,
  author    = {Raul Cernea and
               Long Pham and
               Farookh Moogat and
               Siu Lung Chan and
               Binh Le and
               Yan Li and
               Shouchang Tsao and
               Taiyuan Tseng and
               Khanh Nguyen and
               Jason Li and
               Jayson Hu and
               Jong Park and
               Cynthia Hsu and
               Fanglin Zhang and
               Teruhiko Kamei and
               Hiroaki Nasu and
               Phil Kliza and
               Khin Htoo and
               Jeffery Lutze and
               Yingda Dong and
               Masaaki Higashitani and
               Junhui Yang and
               Hung{-}Szu Lin and
               Vamshi Sakhamuri and
               Alan Li and
               Feng Pan and
               Sridhar Yadala and
               Subodh Taigor and
               Kishan Pradhan and
               James Lan and
               Jim Chan and
               Takumi Abe and
               Yasuyuki Fukuda and
               Hideo Mukai and
               Koichi Kawakami and
               Connie Liang and
               Tommy Ip and
               Shu{-}Fen Chang and
               Jaggi Lakshmipathi and
               Sharon Huynh and
               Dimitris Pantelakis and
               Mehrdad Mofidi and
               Khandker Quader},
  title     = {A 34MB/s-Program-Throughput 16Gb {MLC} {NAND} with All-Bitline Architecture
               in 56nm},
  booktitle = {{ISSCC}},
  pages     = {420--421},
  publisher = {{IEEE}},
  year      = {2008}
}

@inproceedings{DBLP:conf/isscc/KandaKYHYMKMCTCLMTOKFTISNSOKYAHMNYHIKHMIO08,
  author    = {Kazushige Kanda and
               Masaru Koyanagi and
               Toshio Yamamura and
               Koji Hosono and
               Masahiro Yoshihara and
               Toru Miwa and
               Yosuke Kato and
               Alex Mak and
               Siu Lung Chan and
               Frank Tsai and
               Raul Cernea and
               Binh Le and
               Eiichi Makino and
               Takashi Taira and
               Hiroyuki Otake and
               Norifumi Kajimura and
               Susumu Fujimura and
               Yoshiaki Takeuchi and
               Mikihiko Itoh and
               Masanobu Shirakawa and
               Dai Nakamura and
               Yuya Suzuki and
               Yuki Okukawa and
               Masatsugu Kojima and
               Kazuhide Yoneya and
               Takamichi Arizono and
               Toshiki Hisada and
               Shinji Miyamoto and
               Mitsuhiro Noguchi and
               Toshitake Yaegashi and
               Masaaki Higashitani and
               Fumitoshi Ito and
               Teruhiko Kamei and
               Gertjan Hemink and
               Tooru Maruyama and
               Kazumi Ino and
               Shigeo Ohshima},
  title     = {A 120mm\({}^{\mbox{2}}\) 16Gb 4-MLC {NAND} Flash Memory with 43nm
               {CMOS} Technology},
  booktitle = {{ISSCC}},
  pages     = {430--431},
  publisher = {{IEEE}},
  year      = {2008}
}