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Jaehwan Jung
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2010 – 2019
- 2019
- [j8]Seokha Hwang, Seungsik Moon, Jaehwan Jung, Daesung Kim, In-Cheol Park, Jeongseok Ha, Youngjoo Lee:
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4462-4475 (2019) - 2018
- [c4]Jaehwan Jung, In-Cheol Park, Youngjoo Lee:
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. ASP-DAC 2018: 329-330 - [c3]Byeong Yong Kong, Jaehwan Jung, In-Cheol Park:
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. ICECS 2018: 77-80 - 2017
- [j7]Jaehwan Jung, In-Cheol Park:
Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems. IEEE Commun. Lett. 21(5): 979-982 (2017) - [c2]Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee:
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. A-SSCC 2017: 169-172 - 2016
- [j6]Youngjoo Lee, Jaehwan Jung, In-Cheol Park:
Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems. IEICE Trans. Electron. 99-C(2): 293-301 (2016) - [j5]Jaejoon Choi, Jaehwan Jung, In-Cheol Park:
Area-Efficient Approach for Generating Quantized Gaussian Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 1005-1013 (2016) - 2015
- [j4]Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park:
Low-Complexity Tree Architecture for Finding the First Two Minima. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 61-64 (2015) - [j3]Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
Efficient Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1068-1072 (2015) - [c1]Injae Yoo, Mina Hwang, Jaehwan Jung, Suhyun Kim, In-Cheol Park:
Unidirectional ring ethernet for low-complexity in-vehicle control network. ICIT 2015: 1951-1955 - 2013
- [j2]Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park:
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits 48(10): 2531-2540 (2013) - [j1]Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park:
Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 872-876 (2013)
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