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Chao-Chyun Chen
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2020 – today
- 2020
- [j6]Yu-Hsuan Lee, Cheng-Hung Lin, Chao-Chyun Chen, Shu-Yen Lin, Bo-Siang Huang:
Correction to: the Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique. J. Signal Process. Syst. 92(4): 461 (2020)
2010 – 2019
- 2017
- [j5]Yu-Hsuan Lee, Cheng-Hung Lin, Chao-Chyun Chen, Shu-Yen Lin, Bo-Siang Huang:
The Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique. J. Signal Process. Syst. 88(1): 13-27 (2017) - 2016
- [j4]Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang:
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 17-25 (2016) - 2014
- [j3]Yu-Hsuan Lee, Chao-Chyun Chen, Yi-Lun You:
Design of VLSI Architecture of Autocorrelation-Based Lossless Recompression Engine for Memory-Efficient Video Coding Systems. Circuits Syst. Signal Process. 33(2): 459-482 (2014) - [c3]Chun-Yen Wu, Chi-Nan Chuang, Chao-Chyun Chen, I-Chyn Wey:
A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications. GCCE 2014: 352-353 - [c2]Chao-Chyun Chen, Jiun-Wei Yang, Nai-Shen Kuo:
A modified multi-fingers stru cture for power transistor in 0.16μm CMOS process. ICCE-TW 2014: 43-44 - 2012
- [c1]Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen:
A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm. ISPACS 2012: 338-342
2000 – 2009
- 2008
- [j2]Chao-Chyun Chen, Shen-Iuan Liu:
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. IEEE J. Solid State Circuits 43(11): 2413-2421 (2008) - 2007
- [j1]Chao-Chyun Chen, Jung-Yu Chang, Shen-Iuan Liu:
A DLL-Based Variable-Phase Clock Buffer. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1072-1076 (2007)
Coauthor Index
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