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ORCIDKeren Zhu 0001
Person information
- affiliation: Chinese University of Hong Kong, Hong Kong
- affiliation: University of Texas at Austin, ECE Department, TX, USA
Other persons with the same name
- Keren Zhu 0002 — Hubei University of Technology, School of Mechanical Engineering, Wuhan, China
- Keren Zhu 0003
![[0000-0002-1655-7183]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-1655-7183")
— Ohio State University, Department of Electrical and Computer Engineering, Columbus, OH, USA
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2020 – today
- 2024
[j5]Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan:
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 2-15 (2024)- [c29]Hyunsu Chae, Keren Zhu, Bhyrav Mutnury, Zixuan Jiang, Daniel De Araujo, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, David Z. Pan:
ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. ASPDAC 2024: 644-650 - [c28]Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC 2024: 671-678 - [c27]Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, Keren Zhu:
Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). ASPDAC 2024: 679-685 - [c26]Souradip Poddar, Ahmet Faruk Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia, David Z. Pan:
A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing. DATE 2024: 1-6 - [c25]Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu:
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD 2024: 161-168 - [i8]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i7]Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan:
LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. CoRR abs/2406.05250 (2024) - [i6]Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu:
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. CoRR abs/2408.07886 (2024) - [i5]Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng:
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. CoRR abs/2409.08534 (2024) - 2023
- [j4]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits 58(5): 1450-1461 (2023) - [j3]Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2689-2702 (2023) - [j2]Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 715-720 (2023) - [c24]Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan:
ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. DATE 2023: 1-6 - [c23]Ahmet Faruk Budak, Keren Zhu, David Z. Pan:
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. ICCAD 2023: 1-8 - [c22]Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu:
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. ICCAD 2023: 1-9 - [c21]Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren:
Reinforcement Learning Guided Detailed Routing for Custom Circuits. ISPD 2023: 26-34 - [c20]Ahmet Faruk Budak, Keren Zhu, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia, David Z. Pan:
Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities. ISPD 2023: 84-92 - [i4]Ahmet Faruk Budak, Keren Zhu, David Z. Pan:
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks. CoRR abs/2311.17073 (2023) - 2022
- [c19]Keren Zhu, Hao Chen, Mingjie Liu, David Z. Pan:
Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper). ASP-DAC 2022: 108-113 - [c18]Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan:
Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper). ASP-DAC 2022: 500-505 - [c17]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan:
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC 2022: 519-525 - [c16]Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan:
Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. ICCAD 2022: 37:1-37:9 - [c15]Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding from Layouts. ICCAD 2022: 66:1-66:9 - [c14]Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren:
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. ISPD 2022: 175-183 - [i3]Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne C. Incorvia, David Z. Pan:
Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. CoRR abs/2208.08099 (2022) - [i2]Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding From Layouts. CoRR abs/2209.03465 (2022) - 2021
- [j1]Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan:
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [c13]Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan:
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC 2021: 1-2 - [c12]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC 2021: 1-2 - [c11]Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC 2021: 1243-1248 - [c10]Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan:
OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD 2021: 1-9 - [i1]Zixuan Jiang, Jiaqi Gu, Mingjie Liu, Keren Zhu, David Z. Pan:
Optimizer Fusion: Efficient Training with Better Locality and Parallelism. CoRR abs/2104.00237 (2021) - 2020
- [c9]Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c8]Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan:
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC 2020: 1-6 - [c7]Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE 2020: 496-501 - [c6]Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu, David Z. Pan:
An Efficient Training Framework for Reversible Neural Architectures. ECCV (27) 2020: 275-289 - [c5]Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD 2020: 18:1-18:8 - [c4]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD 2020: 133:1-133:9 - [c3]Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan:
Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. MLCAD 2020: 145-150
2010 – 2019
- 2019
- [c2]Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD 2019: 1-8 - [c1]Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD 2019: 1-8
Coauthor Index
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