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2000 – 2009
- 2009
[c51]Eric Cheung, Harry Hsieh, Felice Balarin:
Partial order method for timed simulation of system-level MPSoC designs. ASP-DAC 2009: 149-154- [c50]Eric Cheung, Harry Hsieh, Felice Balarin:
Fast and accurate performance simulation of embedded software for MPSoC. ASP-DAC 2009: 552-557 - [c49]Eric Cheung, Harry Hsieh, Felice Balarin:
Memory subsystem simulation in software TLM/T models. ASP-DAC 2009: 811-816 - 2008
- [c48]Eric Cheung, Harry Hsieh, Felice Balarin:
Software optimization for MPSoC: a mpeg-2 decoder case study. CODES+ISSS 2008: 43-48 - 2007
- [j12]Felice Balarin, Roberto Passerone
:
Specification, Synthesis, and Simulation of Transactor Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1749-1762 (2007) - [c47]Eric Cheung, Harry Hsieh, Felice Balarin:
Framework for fast and accurate performance simulation of multiprocessor systems. HLDVT 2007: 21-28 - [c46]Eric Cheung, Harry Hsieh, Felice Balarin:
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip. HLDVT 2007: 37-44 - [i1]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. CoRR abs/0710.4714 (2007) - 2006
- [j11]Xi Chen, Harry Hsieh, Felice Balarin:
Verification Approach of Metropolis Design Framework for Embedded Systems. Int. J. Parallel Program. 34(1): 3-27 (2006) - [c45]Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli:
Communication and co-simulation infrastructure for heterogeneous system integration. DATE 2006: 462-467 - [c44]Felice Balarin, Roberto Passerone:
Functional verification methodology based on formal interface specification and transactor generation. DATE 2006: 1013-1018 - 2005
- [c43]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE 2005: 92-97 - [c42]Felice Balarin, Roberto Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli:
A formal approach to system level design: metamodels and unified design environments. MEMOCODE 2005: 155-163 - 2004
- [j10]Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin:
Assertion Based Verification and Analysis of Network Processor Architectures. Des. Autom. Embed. Syst. 9(3): 163-176 (2004) - [j9]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1243-1255 (2004) - [c41]Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin:
Utilizing Formal Assertions for System Design of Network Processors. DATE 2004: 126-133 - [c40]Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin:
Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT 2004: 44-53 - [c39]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-based power/performance analysis of network processor architectures. HLDVT 2004: 155-160 - 2003
- [j8]Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli:
Metropolis: An Integrated Electronic System Design Environment. Computer 36(4): 45-52 (2003) - [j7]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. 8(2-3): 139-153 (2003) - [c38]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Case Studies of Model Checking for Embedded System Designs. ACSD 2003: 20-28 - [c37]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic trace analysis for logic of constraints. DAC 2003: 460-465 - [c36]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE 2003: 11174-11175 - [c35]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Verifying LOC based functional and performance constraints. HLDVT 2003: 83-88 - [p1]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC 2003: 275-285 - 2002
- [c34]Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe:
Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design 2002: 228-273 - [c33]Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang:
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES 2002: 13-18 - [c32]Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe:
Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT 2002: 407-416 - [c31]Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal verification of embedded system designs at multiple levels of abstraction. HLDVT 2002: 125-130 - 2001
- [j6]Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Synchronous approach to the functional equivalence of embeddedsystem implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(8): 1016-1033 (2001) - [c30]Felice Balarin:
STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems. CODES 2001: 104-108 - [c29]Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Constraints specification at higher levels of abstraction. HLDVT 2001: 129-133 - [c28]Felice Balarin:
Stars in VCC: Complementing Simulation with Worst-Case Analysis. ICCAD 2001: 471- - [c27]Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin:
Scheduling Reactive Task Graphs in Embedded Control Systems. IEEE Real Time Technology and Applications Symposium 2001: 191-201 - 2000
- [j5]Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1149-1162 (2000) - [c26]Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin:
Task scheduling with RT constraints. DAC 2000: 483-488 - [c25]Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Efficient methods for embedded system design space exploration. DAC 2000: 607-612 - [c24]Felice Balarin:
Automatic Abstraction for Worst-Case Analysis of Discrete Systems. DATE 2000: 494-501 - [c23]Harry Hsieh, Felice Balarin:
Refining abstract equivalence analysis for embedded system design. HLDVT 2000: 139-146
1990 – 1999
- 1999
- [j4]Adnan Aziz, Felice Balarin, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures. Chic. J. Theor. Comput. Sci. 1999 (1999) - [j3]Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki:
Synthesis of software programs for embedded control applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 834-849 (1999) - [c22]Felice Balarin:
Worst-case analysis of discrete systems based on conditional abstractions. CODES 1999: 115-119 - [c21]Felice Balarin:
Worst-case analysis of discrete systems. ICCAD 1999: 347-353 - [c20]Harry Hsieh, Felice Balarin:
Synchronous equivalence for embedded systems: a tool for design exploration. ICCAD 1999: 505-510 - [c19]Felice Balarin, Massimiliano Chiodo:
Software Synthesis for Complex Reactive Embedded Systems. ICCD 1999: 634-639 - [c18]Felice Balarin:
Concurrent Symbolic Verification of Liveness Properties for Interleaved Models. SMC@FLoC 1999: 1-10 - 1998
- [j2]Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli:
Scheduling for Embedded Real-Time Systems. IEEE Des. Test Comput. 15(1): 71-82 (1998) - [c17]Felice Balarin:
Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models. CAV 1998: 391-402 - [c16]Felice Balarin:
Priority Assignment for Embedded Reactive Real-Time Systems. LCTES 1998: 146-155 - 1997
- [c15]Felice Balarin, Massimiliano Chiodo, Attila Jurecska, Luciano Lavagno, Bassam Tabbara, Alberto L. Sangiovanni-Vincentelli:
Automatic Generation of a Real-Time Operating System for Embedded Systems. CODES 1997: 95-100 - [c14]Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
Schedule Validation for Embedded Reactive Real-Time Systems. DAC 1997: 52-57 - [c13]Felice Balarin:
Verifying invariants by approximate image computation. INFINITY 1997: 2-14 - 1996
- [c12]Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Formal Verification of Embedded Systems based on CFSM Networks. DAC 1996: 568-571 - [c11]Felice Balarin:
Approximate reachability analysis of timed automata. RTSS 1996: 52-61 - 1995
- [j1]Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
An Iterative Approach to Verification of Real-Time Systems. Formal Methods Syst. Des. 6(1): 67-95 (1995) - [c10]Adnan Aziz, Vigyan Singhal, Felice Balarin:
It Usually Works: The Temporal Logic of Stochastic Systems. CAV 1995: 155-165 - [c9]Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha:
Supervisory Control of Finite State Machines. CAV 1995: 279-292 - [c8]Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. ICCAD 1995: 612-617 - 1994
- [c7]Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
On the Automatic Computation of Network Invariants. CAV 1994: 234-246 - [c6]Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 - [c5]Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures. ICALP 1994: 364-375 - [c4]Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
Iterative algorithms for formal verification of embedded real-time systems. ICCAD 1994: 450-457 - 1993
- [c3]Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
An Iterative Approach to Language Containment. CAV 1993: 29-40 - [c2]Felice Balarin, Gary York:
Verilog HDL Modeling Styles for Formal Verification. CHDL 1993: 453-465 - 1992
- [c1]Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
A Verification Strategy for Timing-Constrained Systems. CAV 1992: 151-163
Coauthor Index
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