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Journal Articles
- 2013
[j1]Peter Gavin, David B. Whalley, Magnus Själander
:
Reducing instruction fetch energy in multi-issue processors. ACM Trans. Archit. Code Optim. 10(4): 64:1-64:24 (2013)
Conference and Workshop Papers
- 2016
- [c6]Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee:
Redesigning a tagless access buffer to require minimal ISA changes. CASES 2016: 19:1-19:10 - 2015
- [c5]B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
Scheduling instruction effects for a statically pipelined processor. CASES 2015: 167-176 - [c4]Ryan Baird, Peter Gavin, Magnus Själander, David B. Whalley, Gang-Ryung Uh:
Optimizing Transfers of Control in the Static Pipeline Architecture. LCTES 2015: 1:1-1:10 - 2013
- [c3]Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Själander, Per Larsson-Edefors, Sally A. McKee, Per Stenström:
Improving data access efficiency by using a tagless access buffer (TAB). CGO 2013: 28:1-28:11 - [c2]Ian Finlayson, Brandon Davis, Peter Gavin, Gang-Ryung Uh, David B. Whalley, Magnus Själander, Gary S. Tyson:
Improving processor efficiency by statically pipelining instructions. LCTES 2013: 33-44 - 2009
- [c1]Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson:
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). LCTES 2009: 119-128
Coauthor Index
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