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Tariq B. Ahmad

Tariq Bashir Ahmad

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Conference and Workshop Papers

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2014
[c5]
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Tariq B. Ahmad, Maciej J. Ciesielski:
Fast STA prediction-based gate-level timing simulation. DATE 2014: 1-6
[c4]
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Tariq Bashir Ahmad, Maciej J. Ciesielski:
Fast time-parallel C-based event-driven RTL simulation. DDECS 2014: 71-76
[c3]
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Tariq B. Ahmad, Maciej J. Ciesielski:
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ISVLSI 2014: 619-624
2013
[c2]
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Tariq Bashir Ahmad, Maciej J. Ciesielski:
An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads. MTV 2013: 77-82
2011
[c1]
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  - conf/fmcad/BasithARC11
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Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski:
Algebraic approach to arithmetic design verification. FMCAD 2011: 67-71

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