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Pil-Ho Lee

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2020 – today

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2022
[c4]
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  - conf/elinfocom/JangLRCK22
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Chaeyoung Jang, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim:
A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC. ICEIC 2022: 1-2
2021
[c3]
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Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim:
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL. ISOCC 2021: 311-312
2020
[j9]
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Pil-Ho Lee, Young-Chan Jang:
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization. IEEE Trans. Circuits Syst. 67-II(11): 2672-2676 (2020)

2010 – 2019

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2019
[j8]
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Pil-Ho Lee, Young-Chan Jang:
A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(6): 783-787 (2019)
[j7]
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Pil-Ho Lee, Young-Chan Jang:
A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface. IEEE Trans. Consumer Electron. 65(4): 484-492 (2019)
2017
[j6]
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Ho-Seong Kim, Pil-Ho Lee, Jin-Wook Han, Seung-Hun Shin, Seung-Wuk Baek, Doo-Ill Park, Yongkyu Seo, Young-Chan Jang:
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display. IEICE Trans. Electron. 100-C(11): 1035-1038 (2017)
[j5]
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Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong Kim, Han-Young Hong, Young-Chan Jang:
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2. IEEE Trans. Consumer Electron. 63(3): 209-215 (2017)
[j4]
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Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang:
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1386-1396 (2017)
[c2]
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Seung-Hun Shin, Pil-Ho Lee, Jin-Woo Park, Yu-Jeong Hwang, Young-Chan Jang:
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch. ISCAS 2017: 1-4
[c1]
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Jin-Wook Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang:
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver. ISOCC 2017: 246-247
2016
[j3]
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Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang:
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis. IEICE Trans. Electron. 99-C(4): 440-443 (2016)
[j2]
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Sang-Min Park, Yeon-Ho Jeong, Yu-Jeong Hwang, Pil-Ho Lee, Yeong-Woong Kim, Jisu Son, Han-Yeol Lee, Young-Chan Jang:
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators. IEICE Trans. Electron. 99-C(6): 651-654 (2016)
2014
[j1]
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Pil-Ho Lee, Hyun Bae Lee, Young-Chan Jang:
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle. IEICE Trans. Electron. 97-C(5): 463-467 (2014)

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