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Gyu-Seob Jeong
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2020 – today
- 2021
- [j17]Byungjun Kang
, Gyu-Seob Jeong, Jeongho Hwang
, Kwanseo Park
, Hyungrok Do, Hyojun Kim
, Han-Gon Ko
, Moon-Chul Choi
, Deog-Kyoon Jeong
:
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access 9: 156789-156798 (2021) - 2020
- [j16]Jeongho Hwang
, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
:
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1834-1838 (2020)
2010 – 2019
- 2019
- [j15]Han-Gon Ko
, Woo-Rham Bae
, Gyu-Seob Jeong, Deog-Kyoon Jeong
:
Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access 7: 38035-38043 (2019) - [j14]Gyu-Seob Jeong
, Byungjun Kang, Haram Ju, Kwanseo Park
, Deog-Kyoon Jeong
:
A Modulo-FIR Equalizer for Wireline Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4278-4286 (2019) - [c13]Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong:
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. OFC 2019: 1-3 - [c12]Jeongho Hwang
, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong:
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits 2019: 268- - 2018
- [j13]Jeongho Hwang
, Gyu-Seob Jeong, Woo-Rham Bae
, Jun-Eun Park
, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
:
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 436-440 (2018) - [j12]Gyu-Seob Jeong
, Jeongho Hwang
, Hong-Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee
, Kwanseo Park
, Han-Gon Ko
, Kwangho Lee, Jiho Joo
, Gyungock Kim, Deog-Kyoon Jeong
:
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018) - [j11]Hong-Seok Choi, Jeongho Hwang
, Gyu-Seob Jeong
, Gyungock Kim, Deog-Kyoon Jeong
:
A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1824-1828 (2018) - [c11]Jeongho Hwang
, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong:
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. BCICTS 2018: 263-266 - [c10]Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Seong Ho Park, Deog-Kyoon Jeong:
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS. ISLPED 2018: 11:1-11:6 - [c9]Haram Ju, Moon-Chul Choi
, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. VLSI Circuits 2018: 51-52 - 2017
- [j10]Gyu-Seob Jeong, Woo-Rham Bae
, Deog-Kyoon Jeong
:
Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. Sensors 17(9): 1962 (2017) - [j9]Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong:
A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 655-659 (2017) - [j8]Haram Ju, Moon-Chul Choi
, Gyu-Seob Jeong, Woo-Rham Bae
, Deog-Kyoon Jeong
:
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1377-1381 (2017) - 2016
- [j7]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae
, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. IEEE J. Solid State Circuits 51(10): 2312-2327 (2016) - [j6]Woo-Rham Bae
, Gyu-Seob Jeong, Kwanseo Park
, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1393-1403 (2016) - [j5]Yoonsoo Kim, Gyu-Seob Jeong, Jun-Eun Park
, Joonbae Park, Gyungock Kim, Deog-Kyoon Jeong:
20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1034-1038 (2016) - [j4]Woo-Rham Bae
, Gyu-Seob Jeong, Deog-Kyoon Jeong
:
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1106-1110 (2016) - [j3]Woo-Rham Bae
, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong:
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2234-2243 (2016) - [c8]Haram Ju, Woo-Rham Bae
, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. ISCAS 2016: 2346-2349 - [c7]Woo-Rham Bae
, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. ISCAS 2016: 2906 - 2015
- [j2]Sang-Hyeok Chu, Woo-Rham Bae
, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015) - [j1]Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 836-840 (2015) - [c6]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae
, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC 2015: 1-4 - [c5]Kwanseo Park
, Woo-Rham Bae
, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS 2015: 2389-2392 - [c4]Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. VLSIC 2015: 136- - 2014
- [c3]Sang-Hyeok Chu, Woo-Rham Bae
, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC 2014: 101-104 - [c2]Woo-Rham Bae
, Gyu-Seob Jeong, Kwanseo Park
, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450 - [c1]Gyu-Seob Jeong, Hankyu Chi, Kyungock Kim, Deog-Kyoon Jeong:
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS. ISCAS 2014: 1492-1495
Coauthor Index
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last updated on 2024-08-03 20:14 CEST by the dblp team
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