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Journal Articles
- 2012
[j13]Koyo Nitta
, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma:
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Trans. Electron. 95-C(4): 432-440 (2012)- 2010
- [j12]Takeshi Yoshitome, Jiro Naganuma, Yoshiyuki Yashima:
MPEG-2 Transcoding Method for Reducing Re-quantization Noise Based on a Two-tiered Quantizer Matrix. Inf. Media Technol. 5(1): 129-138 (2010) - 2008
- [j11]Takeshi Yoshitome, Ken Nakamura, Jiro Naganuma, Yoshiyuki Yashima:
A Flexible Video CODEC System for Super High Resolution Video. IEICE Trans. Inf. Syst. 91-D(11): 2709-2717 (2008) - [j10]Takayuki Onishi, Ken Nakamura, Takeshi Yoshitome, Jiro Naganuma:
A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV. IEICE Trans. Inf. Syst. 91-D(12): 2862-2867 (2008) - 2007
- [j9]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1055-1059 (2007) - 2006
- [j8]Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
Highly accurate de-jittering scheme for broadcast quality video transmission. Syst. Comput. Jpn. 37(10): 81-88 (2006) - 2005
- [j7]Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks. Syst. Comput. Jpn. 36(2): 33-41 (2005) - [j6]Minoru Inamori, Hiroe Iwasaki, Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Yoshiyuki Yashima:
New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI. IEEE Trans. Consumer Electron. 51(2): 640-641 (2005) - 2002
- [j5]Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
Advanced concurrent design environment for multimedia system LSIs. Syst. Comput. Jpn. 33(14): 72-80 (2002) - 1999
- [j4]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai:
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19(4): 56-65 (1999) - [j3]Minoru Inamori, Jiro Naganuma, Makoto Endo:
A memory-based architecture for MPEG2 system protocol LSIs. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 339-344 (1999) - 1994
- [j2]Jiro Naganuma, Takeshi Ogura:
A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms. IEEE Trans. Computers 43(9): 1062-1075 (1994) - 1988
- [j1]Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura:
High-Speed CAM-Based Architecture for a Prolog Machine (ASCA). IEEE Trans. Computers 37(11): 1375-1383 (1988)
Conference and Workshop Papers
- 2008
- [c9]Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma:
Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. ISCAS 2008: 800-803 - 2004
- [c8]Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. ISCAS (2) 2004: 261-264 - 2003
- [c7]Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo:
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. CICC 2003: 177-180 - [c6]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE 2003: 20002-20007 - 1999
- [c5]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. DATE 1999: 44- - [c4]Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. DATE 1999: 303-308 - [c3]Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. RTCSA 1999: 200-203 - 1996
- [c2]Minoru Inamori, Jiro Naganuma, Haruo Wakabayashi, Makoto Endo:
A Memory-based Architecture for MPEG2 System Protocol LSIs. ED&TC 1996: 500-507 - 1994
- [c1]Jiro Naganuma, Takeshi Ogura, Tamio Hoshino:
High-Level Design Validation Using Algorithmic Debugging. EDAC-ETC-EUROASIC 1994: 474-480
Coauthor Index
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