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2010 – 2019
- 2017
[j13]Yeon-Jin Kim, In-Gul Jang, Kyung-Ju Cho, Jin-Gyun Chung:
Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE. IEICE Electron. Express 14(12): 20170395 (2017)- 2016
- [c7]Yeon-Jin Kim, Zhe-Yan Piao, Jin-Gyun Chung, In-Gul Jang, Kyung-Ju Cho:
Low latency IFFT design for 3GPP LTE. ISOCC 2016: 69-70 - 2014
- [j12]Ho-Yun Lee, Jun-Ho Kim, In-Gul Jang, Kyung-Ju Cho, Jin-Gyun Chung:
Memory efficient DIT-based SDF IFFT for OFDM systems. IEICE Electron. Express 11(5): 20140010 (2014) - 2013
- [j11]In-Gul Jang, Kyung-Ju Cho, Hwan-Yong Kim, Jin-Gyun Chung:
Memory efficient IFFT design for OFDM-based applications. IEICE Electron. Express 10(21): 20130530 (2013) - 2012
- [j10]Kyung-Ju Cho:
Efficient unsigned squarer design techniques. IEICE Electron. Express 9(6): 422-428 (2012) - [j9]In-Gul Jang, Kyung-Ju Cho, Yong-Eun Kim, Jin-Gyun Chung:
Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications. IEICE Trans. Commun. 95-B(6): 2059-2064 (2012) - [c6]In-Gul Jang, Dae-Ho Kim, Ho-Yun Yi, Jin-Gyun Chung, Kyung-Ju Cho:
Efficient IFFT architecture design for OFDM applications. ISOCC 2012: 231-234 - 2011
- [j8]In-Gul Jang, Kyung-Ju Cho:
A memory size reduction method of pipelined IFFT processor for OFDM systems. IEICE Electron. Express 8(19): 1627-1632 (2011) - [c5]Kyung-Ju Cho, Jin-Gyun Chung, Hwan-Yong Kim, Gwang-Jun Kim, Dae-Ik Kim, Yong-Kab Kim:
Fixed-Width Modified Booth Multiplier Design Based on Error Bound Analysis. FGIT-MulGraB (2) 2011: 248-256 - 2010
- [j7]Yong-Eun Kim, Kyung-Ju Cho, Jin-Gyun Chung, Xinming Huang:
CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(1): 324-326 (2010) - [j6]Yong-Eun Kim, Kyung-Ju Cho, Jin-Gyun Chung, Xinming Huang:
Fixed-Width Group CSD Multiplier Design. IEICE Trans. Inf. Syst. 93-D(6): 1497-1503 (2010) - [j5]Yi-Nan Xu, Yong-Eun Kim, Kyung-Ju Cho, Jin-Gyun Chung, Xinming Huang:
Implementation of FlexRay CC and BG protocols with application to a robot system. Int. J. Comput. Aided Eng. Technol. 2(1): 112-122 (2010)
2000 – 2009
- 2008
- [c4]Kyung-Ju Cho, Suhyun Jo, Yong-Eun Kim, Yi-Nan Xu, Jin-Gyun Chung:
Constant multiplier design using specialized bit pattern adders. ICECS 2008: 41-44 - [c3]Yi-Nan Xu, Yong-Eun Kim, Kyung-Ju Cho, Jin-Gyun Chung, Myoung-Seob Lim:
Implementation of FlexRay communication controller protocol with application to a robot system. ICECS 2008: 994-997 - [c2]Yinan Xu, Hyunsoo Kang, Yongeun Kim, Kyungju Cho, Jingyun Chung:
Implementation of FlexRay CC and BG Protocols with Application to a Robot System. MSV 2008: 232-237 - 2007
- [j4]Kyung-Ju Cho, Jin-Gyun Chung:
Adaptive Error Compensation for Low Error Fixed-Width Squarers. IEICE Trans. Inf. Syst. 90-D(3): 621-626 (2007) - [j3]Yong-Eun Kim, Kyung-Ju Cho, Jin-Gyun Chung:
Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(3): 694-697 (2007) - [j2]Kyung-Ju Cho, Ji-Suk Park, Byeong-Kuk Kim, Jin-Gyun Chung, Keshab K. Parhi
:
Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 19-23 (2007) - [c1]Kyung-Ju Cho, Yi-Nan Xu, Jin-Gyun Chung:
Hardware Efficient QR Decomposition for GDFE. SiPS 2007: 412-417 - 2004
- [j1]Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Keshab K. Parhi:
Design of low-error fixed-width modified booth multiplier. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 522-531 (2004)
Coauthor Index
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