Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA.

Mon, 01 Jan 2018 00:00:00 +0100

Junsong Wang, Qiuwen Lou, Xiaofan Zhang, Chao Zhu, Yonghua Lin, Deming Chen:
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA. FPL 2018: 163-169